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COMPLETE COURSE LIST

CourseCommon TopicsPersonaSiliconStatus
Designing with the Versal ACAP: Architecture and MethodologyArchitecture, Tools, Simulation, Debugging, Versal, PetaLinuxHardware Engineer, Software Engineer, System ArchitectFPGA, ACAP, SoCCurrent
Designing with the Versal ACAP: Network on ChipArchitecture, Versal, Memory, I/O, DebuggingHardware Engineer, Software Engineer, System ArchitectACAPCurrent
Designing with the Versal ACAP: Power and BoardSignal Integrity, Versal, PowerHardware Engineer, System ArchitectACAPCurrent
Designing with Versal AI Engine 1: Architecture and Design FlowVersal, Architecture, Tools, EmbeddedHardware Engineer, Software Engineer, System ArchitectACAP, AICurrent
Designing with Versal AI Engine 2: Graph Programming with AI Engine KernelsVersal, Tools, Debugging, EmbeddedSoftware Engineer, System ArchitectACAP, AICurrent
Designing with Versal AI Engine 3: Kernel Programming and OptimizationVersal, Debugging, EmbeddedSoftware Engineer, System ArchitectACAP, AICurrent
Vitis Model Composer: A MATLAB and Simulink-based ProductVitis, DSP, HLS, AI, MATLABHardware Engineer, System ArchitectFPGA, ACAP, AICurrent
Accelerating Applications with the Vitis Unified Software EnvironmentTools, Vitis, EmbeddedSoftware Engineer, System ArchitectFPGA, ACAP, SoC, AICurrent
Developing AI Inference Solutions with the Vitis AI PlatformVitis, MLSoftware EngineerAICurrent
BLT Exclusive: Embedded Systems Hardware Design Boot CampVivado, MPSoC, Zynq UltraScale+, Debugging, ToolsHardware Engineer, Software Engineer, System ArchitectSoCCurrent
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials - Architecture, Memory and IOArchitecture, Memory, I/O, Clocking, Ultrascale, ToolsHardware EngineerFPGACurrent
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingVivado, Tcl, Tools, Clocking, Debugging, Timing Constraints, SimulationHardware EngineerFPGACurrent
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing ClosureVivado, Timing Constraints, Clocking, DebuggingHardware EngineerFPGACurrent
BLT Exclusive: Vivado Boot Camp: Basic TrainingArchitecture, Vivado, Tools, Timing ConstraintsHardware EngineerFPGACurrent

BLT Exclusive: Spartan-6 / ISE User Migration Training

Vivado, Tcl, Tools, Clocking, Debugging, Timing Constraints, SimulationHardware EngineerFPGACurrent
BLT Exclusive: Designing an Integrated PCI Express System with Xilinx Serial TransceiversConnectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIe, Embedded, Signal IntegrityHardware Engineer, System ArchitectFPGADeprecated

BLT Exclusive: Advanced Debug Techniques for Hardware Engineers

Debugging, Vivado, ToolsHardware Engineer, System ArchitectFPGA, SoCCurrent

BLT Exclusive: Advanced Debugging Workshop (Sponsored by AMD - Xilinx)

Debugging, Vivado, Tools, Spartan-6 MigrationHardware Engineer, System ArchitectFPGA, SoCCurrent
Designing an Integrated PCI Express SystemConnectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIeHardware Engineer, Software Engineer, System ArchitectFPGACurrent
Design Closure TechniquesFPGA, Vivado, Timing Closure, Test Bench, Simulation, Design ClosureHardware Engineer, Software Engineer, System ArchitectFPGA, ACAPCurrent
Designing with UltraScale FPGA TransceiversSignal Integrity, Testbench, DebuggingHardware EngineerFPGACurrent
Designing with Xilinx Serial TranscieversSignal Integrity, Testbench, DebuggingHardware EngineerFPGACurrent
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteTools, Debugging, partial reconfigurationHardware EngineerFPGACurrent
Signal Integrity and Board Design for Xilinx FPGAsSignal Integrity, Clocking, Simulation, VerificationHardware EngineerFPGACurrent
BLT Exclusive: Essential DSP Design Techniques using System GeneratorDSP, Tools, Verification, SimulationHardware Engineer, System ArchitectFPGADeprecated
DSP Design Using System GeneratorDSP, Tools, Verification, SimulationHardware Engineer, System ArchitectFPGADeprecated
Essential DSP Implementation Techniques for Xilinx FPGAsDSP, Tools, Verification, SimulationHardware Engineer, System ArchitectFPGACurrent
Designing FPGAs Using the Vivado Design Suite 1Architecture, Vivado, Timing Constraints, Debugging, Tools, Clocking, TclHardware EngineerFPGACurrent
Designing FPGAs Using the Vivado Design Suite 2Vivado, Debugging, Tcl, Timing Constraints, ClockingHardware EngineerFPGACurrent
Designing FPGAs Using the Vivado Design Suite 3Debugging, Timing Constraints, Vivado, Clocking, TclHardware EngineerFPGACurrent
Designing FPGAs Using the Vivado Design Suite 4Debugging, Timing Constraints, Vivado, Clocking, TclHardware EngineerFPGACurrent
Xilinx Partial Reconfiguration Tools & TechniquesTools, Debugging, Partial ReconfigurationHardware EngineerFPGACurrent
Designing with the UltraScale and UltraScale+ ArchitecturesUltraScale+, UltraScale, Architecture, Clocking, DSPHardware Engineer, System ArchitectFPGACurrent
Advanced VHDLRTL, Testbench, Simulation, LanguageHardware Engineer, System ArchitectFPGA, SoCCurrent
BLT Exclusive: Designing and Verification with SystemVerilogRTL, Testbench, Simulation, Language, VerificationHardware Engineer, System ArchitectFPGACurrent
Designing with SystemVerilogRTL, LanguageHardware Engineer, System ArchitectFPGACurrent
Designing with VerilogRTL, Testbench, Simulation, LanguageHardware Engineer, System ArchitectFPGACurrent
Designing with VHDLRTL, Testbench, Simulation, LanguageHardware Engineer, System ArchitectFPGACurrent
Verification with SystemVerilogRTL, LanguageHardware Engineer, System ArchitectFPGACurrent
High-Level Synthesis with the Vitis HLS ToolVitis, Tools, Testbench, Zynq UltraScale+, MPSoC, RTL, HLSHardware Engineer, Software Engineer, System ArchitectFPGA, SoCCurrent
Designing with the Zynq UltraScale+ RFSoCRFSoC, Simulation, Zynq UltraScale+Hardware Engineer, Software Engineer, System ArchitectFPGA, SoCCurrent
Embedded Design with PetaLinux ToolsZynq UltraScale+, MPSoC, Versal, Embedded, Tools, DebuggingSoftware Engineer, System ArchitectSoCCurrent
Zynq UltraScale+ MPSoC for the Hardware DesignerZynq UltraScale+, MPSoC, Tools, VivadoHardware EngineerFPGA, SoCCurrent
Zynq UltraScale+ MPSoC for the Software DeveloperZynq UltraScale+, MPSoC, Embedded, Tools, DebuggingSoftware EngineerSoCCurrent
Zynq UltraScale+ MPSoC for the System ArchitectZynq UltraScale+, MPSoC, Embedded, Tools, DebuggingSystem ArchitectFPGA, SoCCurrent
Xilinx for ManagersArchitecture, Tools, MethodologiesManagerFPGA, SoC, ACAPCurrent
PCIe Protocol OverviewPCIe, Debugging, Embedded, ConnectivityHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecated

C-based Design: High-Level Synthesis with the Vivado HLx Tool

Vitis, Tools, Testbench, RTL, HLSHardware Engineer, Software Engineer, System ArchitectFPGADeprecated
Designing with the Xilinx 7 Series FamiliesArchitecture, Clocking, DSPHardware Engineer, System ArchitectFPGA, SoCDeprecated
Developing and Optimizing Applications Using the OpenCL Framework for FPGAsOpenCL, Debugging, EmbeddedHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecated
Embedded Systems DesignEmbedded, Zynq, Vivado, Tools, SimulationHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecated
Embedded Systems Software DesignEmbedded, Zynq, Vivado, Tools, DebuggingSoftware EngineerSoCDeprecated
How to Design a High-Speed Memory InterfaceMemory, I/O, Debugging, Tools, TestbenchHardware EngineerFPGADeprecated
Migrating to the Vitis Embedded Software Development IDE WorkshopVitis, Tools, Debugging, EmbeddedHardware Engineer, Software Engineer, System ArchitectSoCDeprecated
UltraFast Design MethodologyVivado, Tools, Timing Constraints, I/OHardware Engineer, System ArchitectFPGADeprecated
Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software UsersVivado, Tools, Timing Constraints, TclHardware EngineerFPGADeprecated
Vivado Design Suite for ISE Software Project Navigator UsersVivado, Tools, Simulation, Timing ConstraintsHardware EngineerFPGADeprecated
Zynq All Programmable SoC System ArchitectureZynq, Memory, I/O, ArchitectureHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecated
Advanced Features and Techniques of Embedded Systems DesignEmbedded, Vivado, Simulation, VerificationHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecated
Advanced SDSoC Development Environment and MethodologyArchitecture, Memory, Vivado, ToolsHardware Engineer, Software Engineer, System ArchitectSoCDeprecated
Designing with Ethernet MAC ControllersEthernet, Simulation, Vivado, Testbench, I/OHardware EngineerFPGADeprecated
Designing with the Spartan-6 and Virtex-6 FPGA FamiliesArchitecture, Spartan-6, Vivado, Tools, Clocking Hardware Engineer, System ArchitectFPGADeprecated

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

All in all a great experience.

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2