Zynq® All Programmable SoC System Architecture

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

Please contact the BLT Training Team to schedule a private class.

The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq® All Programmable SoC.

This course presents the features and benefits of the Zynq® architecture for making decisions on how to best architect a Zynq® All Programmable SoC project. It covers the architecture of the ARM Cortex®-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq® All Programmable SoC.

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the architecture and components that comprise the Zynq® All Programmable SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq® All Programmable SoC
  • Effectively select and design an interface between the Zynq® PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Course Outline

Day 1

  • Zynq® All Programmable SoC Overview
  • Inside the Application Processor Unit (APU)
  • LAB: Building a Zynq® All Programmable SoC Platform
    Examine the process of using the Vivado IP Integrator tool to create a simple processing system.
  • Processor Input/Output Peripherals
  • Introduction to AXI
  • Zynq® All Programmable SoC PS-PL Interfaces
  • LAB: Integrating Programmable Logic on the Zynq® All Programmable SoC
    Connect a programmable logic (PL) design to the embedded processing system (PS).
  • Zynq® All Programmable SoC Booting
  • LAB: Using DMA on the Zynq® All Programmable SoC
    Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.

Day 2

  • Zynq® All Programmable SoC Memory Resources
  • Meeting Performance Goals
  • LAB: Impact of Port Selection on System Performance
    Explore bandwidth issues surrounding the use of the Accelerator Coherency Port (ACP) and the High Performance (HP) ports.
  • Zynq® All Programmable SoC Hardware Design
  • Zynq® All Programmable SoC Software Design
  • Debugging the Zynq® All Programmable SoC
  • LAB: Debugging on the Zynq® All Programmable SoC
    Evaluate debugging the hardware and software components of a Zynq® All Programmable SoC design.
  • Zynq® All Programmable SoC Tools and Reference Designs
  • LAB: Running and Debugging a Linux Application on the Zynq® All Programmable SoC
    Explore a software application executing under the Linux operating system on the Zynq® All Programmable SoC.

Training Duration:

2 Days

Who should attend:

System architects who are interested in architecting a system on a chip using the Zynq® All Programmable SoC.


  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Version: 2021-03-17_0932