Zynq SoC System Architecture

This course is available as private training only.

COURSE CODE: EMBD-ZSA

Provides experienced system architects with the knowledge on how to best architect an AMD Zynq System on a Chip (SoC) device project.

This course covers:

  • Identifying the features and benefits of the Zynq SoC architecture
  • Describing the architecture of the Arm Cortex-A9 processor-based processing system (PS) and the connections to the programmable logic (PL)
  • Detailing the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupts, and memory controllers
  • Effectively accessing and using the PS DDR controller from PL user logic
  • Interfacing PL-to-PS connections efficiently
  • Employing best practice design techniques for implementing functions in the PS or PL

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$120012
In-Person Public Registration - $600/day$120012
Printed Course Book (A PDF book is included in the course fee)$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

2 Days

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

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Who should attend:

System architects who are interested in architecting a system on a chip using the SoC.

Software Tools

  • Vivado Design Suite
  • Vitis unified software platform

Hardware

  • Architecture: Zynq-7000 SoC*
  • Demo board: Zynq-7000 SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 SoC.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq SoC
  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Course Outline

Day 1Day 2
Overview
Provides a general overview of the Zynq SoC. {Demo}

Application Processor Unit (APU)
Explores the individual components that comprise the APU. {Lab}

Neon Co-Processor
Describes the Neon co-processor that is the companion to each Cortex-A9 processor.

Input/Output Peripherals
Introduces the components that comprise the IOP block of the Zynq device PS. {Demo}

PS Peripherals
  • Low-Speed: Overview: Introduces the low-speed peripherals in the Zynq SoC. {Lab} 
  • Low-Speed: UART: Introduces the UART low-speed peripheral. {Demo}
  • Low-Speed: CAN: Introduces the CAN low-speed peripheral. {Demo}
  • Low-Speed: I2C: Introduces the I2C low-speed peripheral.
  • Low-Speed: SD/SDIO: Introduces the SD/SDIO low-speed peripheral.
  • Low-Speed: SPI: Introduces the SPI low-speed peripheral.
  • Low-Speed: GPIO: Introduces the GPIO low-speed peripheral.
  • High-Speed: USB: Introduces the USB high-speed peripheral.
  • High-Speed: Gigabit Ethernet: Introduces the Gigabit Ethernet high-speed peripheral. {Lab}

DMA Controller (DMAC)
Explores the operation of the DMAC, which is located in the APU. {Lab}

DMA
  • Introduction and Features: Introduces the direct memory access controller.
  • Block Design and Interrupts: Introduces the DMA block design and the DMA interrupts.
  • Read and Write: Introduces the concepts behind DMA reading and writing.
AXI
  • Introduction: Introduces the AXI protocol.
  • Variations: Describes the differences and similarities among the three primary AXI variations.
  • Transactions: Describes different types of AXI transactions. {Demo, Lab}

PS-PL Interface
Describes in detail the PS interconnect and how it affects PL architecture decisions. {Demo, Lab}

Memory Resources
Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS. {Demo}

Booting
Explains the boot process of the PC and configuration of the PL. {Lab}

Meeting Performance Goals
Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques. {Lab}

Hardware Design
Discusses the use and configuration of the PS in a hardware design.

Software Design
Explores the software side of the Zynq device. {Demo, Lab}

Debugging
Introduces debug tools and methodology on the Zynq SoC. {Lab}

Tools and Reference Designs
Describes Xilinx-provided reference design platforms, use cases, and third-party operating systems and tools for the Zynq SoC.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

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Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.