Dynamic Function eXchange (DFX) Using the Vivado Design Suite
Dynamic Function eXchange (DFX) Using the Vivado Design Suite (formerly Partial Reconfiguration)
Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.
The emphasis of this course is on:
- Identifying best design practices and understanding the subtleties of the DFX design flow
- Using the DFX Controller and DFX Decoupler IP in the DFX process
- Implementing DFX in an embedded system environment
- Applying appropriate debugging techniques on DFX designs
- Employing best practice coding styles for a DFX system
| 2-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $299/day | $598 | 6 |
| In-Person Registration - $399/day | $798 | 8 |
| Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
| Private Training | Contact Us | Contact Us |
| Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
Live Online Training (9am-5pm ET)
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Who should attend:
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx® design methodology and who want to learn partial reconfiguration techniques.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe what Dynamic Function eXchange is
- Define DFX regions and Reconfigurable Modules with the Vivado Design Suite
- Generate the appropriate full and partial bitstreams for a DFX design
- Implement a nested DFX design
- Use the ICAP and PCAP components to deliver the partially reconfigurable systems
- Implement a DFX system using the DFX Controller IP
- Identify how Dynamic Function eXchange affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
Course Outline
| Day 1 | Day 2 |
|---|---|
Basics of DFX
| DFX Configuration
|
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO
- Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging
- Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure
- Working HDL knowledge (Designing with VHDL or Designing with Verilog)
RELATED COURSES:
- Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO
- Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging
- Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure
- Designing with VHDL
- Designing with Verilog