Dynamic Function eXchange (DFX) Using the Vivado Design Suite (formerly Partial Reconfiguration)

Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.

The emphasis of this course is on:

  • Identifying best design practices and understanding the subtleties of the DFX design flow
  • Using the DFX Controller and DFX Decoupler IP in the DFX process
  • Implementing DFX in an embedded system environment
  • Applying appropriate debugging techniques on DFX designs
  • Employing best practice coding styles for a DFX system

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$5986
In-Person Registration - $399/day$7988
Printed Course Book (mailed to you)$1001
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Scheduled Classes

Training Duration:

2 Days

We update our schedule regularly. Stay informed.

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx® design methodology and who want to learn partial reconfiguration techniques.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe what Dynamic Function eXchange is
  • Define DFX regions and Reconfigurable Modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a DFX design
  • Implement a nested DFX design
  • Use the ICAP and PCAP components to deliver the partially reconfigurable systems
  • Implement a DFX system using the DFX Controller IP
  • Identify how Dynamic Function eXchange affects various silicon resources, including block RAM, IOBs, fabric, and MGTs

Course Outline

Day 1Day 2
Basics of DFX
  • Introduction to Dynamic Function eXchange (DFX): Explains what Dynamic Function eXchange is and defines the terminologies used in DFX. Also provides an overview of the configuration and reconfiguration processes. {Lecture, Demo}
    DFX Tool Flow
    • DFX Flow Using the Vivado Design Suite GUI: Illustrates the steps for creating a DFX project in the Vivado Design Suite and describes various supported and unsupported features. {Lecture, Lab}
    • DFX Flow Using Vivado Design Suite Tcl Commands: Reviews the flow using non-project-based commands, including using implementation constraints and specific characteristics {Lecture, Lab}
    • Nested DFX: Describes using nested DFX, the process by which a Reconfigurable Partition (RP) can be segmented into smaller regions, each of which is partially reconfigurable. {Lecture, Lab}
    • Abstract Shell for Dynamic Function eXchange:  Describes how compilation time can be reduced by using an Abstract shell (UltraScale+ devices only). {Lecture}
    DFX Design Considerations for Xilinx Devices
    • DFX Design Considerations for All Xilinx Devices: Covers the requirements, characteristics, and limitations associated with DFX designs that can simplify the debug process and reduce the risk of design malfunctions. {Lecture}
    • DFX Design Considerations for 7 Series, Zynq SoC, UltraScale, and UltraScale+ Devices:  Discusses DFX design consideration methodologies for various Xilinx device families. {Lecture}
    DFX Design-Specific IP Blocks
    • DFX Intellectual Property (IP): Reviews the various IPs that are specifically for use with with DFX designs. {Lecture, Lab, Demo}
    DFX Configuration
    • Configuring Devices Using DFX Reviews the basics of configuration and various configuration modes. {Lecture}
    • Configuration Parameters: Covers various configuration parameters, including factors that affect configuration time and configuration debugging. {Lecture}
    • DFX Bitstreams: Describes the different types of bitstreams for DFX compilation, including full, partial, blanking, and clearing. {Lecture}

    Please note: The instructor may change the content order to provide a better learning experience.

    Updated 12-08-2021