Designing with the Xilinx 7 Series Families
Designing with the Xilinx 7 Series Families
DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.
Please contact the BLT Training Team to schedule a private class.
Are you interested in learning how to effectively utilize Xilinx 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Vivado Boot Camp: Basic Training course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.
Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
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Who should attend:
For those who have taken the Vivado Boot Camp: Basic Training course.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series FPGAs
- Specify the CLB resources and the available slice configurations for the 7 series FPGAs
- Define the block RAM, FIFO, and DSP resources available for the 7 series FPGAs
- Properly design for the I/O block and SERDES resources
- Identify the MMCM, PLL, and clock routing resources included with these families
- Identify the hard resources available for implementing high performance DDR3 physical layer interfaces
- Describe the additional dedicated hardware for all the 7 series family members
- Properly code your HDL to get the most out of the 7 series FPGAs
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Vivado Boot Camp: Basic Training course
- Intermediate VHDL or Verilog knowledge