Check out the latest classes on the BLT Training Calendar

We provide a range of courses including hands-on labs, interactive discussions & best practices to leverage your success. We offer online and in-person training, as well as private training. Our BLT training center is located in Columbia, MD. Class location is noted on the calendar.

View the calendar below or find a class another way:

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ATP 2022 Number 1

COURSE SCHEDULE

COURSECLASS DATELOCATIONSTATUS
Webinar: Interfacing DDR with Programmable Logic on the Versal NoCOn-DemandRecordedWatch
Webinar: Xilinx for ManagersOn-DemandRecordedWatch
Webinar: Accelerating AI with the Vitis Unified Software PlatformOn-DemandRecordedWatch
Webinar: Debugging Using Cross TriggeringOn-DemandRecordedWatch
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteAugust 30-31, 2022Live E-LearningClosed
BLT Exclusive: Advanced Debugging Workshop (Sponsored by AMD - Xilinx)September 1, 2022Live E-LearningClosed
Essential DSP Implementation Techniques for Xilinx FPGAsSeptember 13, 2022Live E-LearningClosed
NEW! Vitis Model Composer: A MATLAB and Simulink-based ProductSeptember 14-15, 2022Live E-LearningClosed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCSeptember 20-21, 2022Live E-LearningClosed
Designing with the ZynqUltraScale+ RFSoCSeptember 20-21, 2022Live E-LearningClosed
Embedded Design with PetaLinux ToolsSeptember 27-28, 2022Live E-Learning8 seats left
Designing with VHDLOctober 4-6, 2022Live E-LearningClosed
Designing with VerilogOctober 11-13, 2022Live E-Learning7 seats left
Designing with the Versal ACAP: Architecture and MethodologyOctober 18-21, 2022Live E-Learning4 seats left
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials - Architecture, Memory and IOOctober 25-27, 2022Live E-Learning3 seats left
BLT Exclusive: Xilinx for ManagersOctober 26, 2022Live E-Learning7 seats left
High-Level Synthesis with the Vitis HLS ToolNovember 1-2, 2022Live E-LearningConfirmed
Designing and Verification with SystemVerilogNovember 1-3, 2022Live E-LearningConfirmed
BLT Exclusive: Vitis Model Composer No-Cost Workshop (Sponsored by AMD - Xilinx)November 3, 2022Live E-LearningLIMITED SEATS
Designing with the Versal ACAP: Network on ChipNovember 8, 2022Live E-Learning9 seats left
Designing with Versal AI Engine 1November 9-10, 2022Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingNovember 15-17, 2022Live E-Learning3 seats left
BLT Exclusive: Spartan-6 / ISE User Migration TrainingNovember 15-17, 2022Live E-Learning5 seats left
Essential DSP Implementation Techniques for Xilinx FPGAsNovember 29, 2022Live E-LearningConfirmed
NEW! Vitis Model Composer: A MATLAB and Simulink-based ProductNovember 30 - December 1, 2022Live E-Learning9 seats left
Designing with Versal AI Engine 2December 6-7, 2022Live E-LearningConfirmed
Designing with the Versal ACAP: Power and Board DesignDeccember 8, 2022Live E-LearningConfirmed
BLT Exclusive: Advanced Debugging Workshop (Sponsored by AMD - Xilinx)Deccember 8, 2022Live E-LearningConfirmed
Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing ClosureDecember 13-15, 2022Live E-Learning3 seats left
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteJanuary 10-11, 2023Live E-LearningConfirmed
BLT Exclusive: Advanced Debug Techniques for Hardware EngineersJanuary 12, 2023Live E-LearningConfirmed
BLT Exclusive: Xilinx for ManagersJanuary 17, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 3: Kernel Programming and OptimizationJanuary 18-19, 2023Live E-LearningConfirmed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCJanuary 24-26, 2023Live E-LearningConfirmed
Designing with the Zynq UltraScale+ RFSoCJanuary 31 - February 1, 2023Live E-LearningConfirmed
Embedded Design with PetaLinux ToolsFebruary 7-8, 2023Live E-Learning9 seats left
Designing with VHDLFebruary 14-16, 2023Live E-LearningConfirmed
Designing with VerilogFebruary 21-23, 2023Live E-LearningConfirmed
Designing with the Versal ACAP: Architecture and MethodologyFebruary 28 - March 2, 2023Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IOMarch 7-9, 2023Live E-LearningConfirmed
High-Level Synthesis with the Vitis HLS ToolMarch 14-15, 2023Live E-LearningConfirmed
BLT Exclusive: Designing and Verification with SystemVerilogMarch 14-16, 2023Live E-LearningConfirmed
Designing with the Versal ACAP: Network on ChipMarch 21, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 1March 22-23, 2023Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingMarch 28-30, 2023Live E-LearningConfirmed
BLT Exclusive: Spartan-6 / ISE User Migration TrainingMarch 28-30, 2023Live E-LearningConfirmed
Essential DSP Implementation Techniques for Xilinx FPGAsApril 4, 2023Live E-LearningConfirmed
Vitis Model Composer: A MATLAB and Simulink-based ProductApril 5-6, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 2April 11-12, 2023Live E-LearningConfirmed
Designing with the Versal ACAP: Power and Board DesignApril 13, 2023Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing ClosureApril 18-20, 2023Live E-LearningConfirmed
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteApril 25-26, 2023Live E-LearningConfirmed
BLT Exclusive: Advanced Debug Techniques for Hardware EngineersApril 25, 2023Live E-LearningConfirmed
BLT Exclusive: Xilinx for ManagersMay 2, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 3: Kernel Programming and OptimizationMay 3-4, 2023Live E-LearningConfirmed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCMay 9-11, 2023Live E-LearningConfirmed
Designing with the Zynq® UltraScale+™ RFSoCMay 16-17, 2023Live E-LearningConfirmed
Embedded Design with PetaLinux ToolsMay 23-24, 2023Live E-LearningConfirmed
Designing with VHDLJune 6-8, 2023Live E-LearningConfirmed
Designing with VerilogJune 13-15, 2023Live E-LearningConfirmed
Designing with the Versal ACAP: Architecture and MethodologyJune 20-22, 2023Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IOJune 27-29, 2023Live E-LearningConfirmed
High-Level Synthesis with the Vitis HLS ToolJuly 18-19, 2023Live E-LearningConfirmed
BLT Exclusive: Designing and Verification with SystemVerilogJuly 18-20, 2023Live E-LearningConfirmed
Designing with the Versal ACAP: Network on ChipJuly 25, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 1July 26-27, 2023Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingAugust 1-3, 2023Live E-LearningConfirmed
BLT Exclusive: Spartan-6 / ISE User Migration TrainingAugust 1-3, 2023Live E-LearningConfirmed
Essential DSP Implementation Techniques for Xilinx FPGAsAugust 8, 2023Live E-LearningConfirmed
Vitis Model Composer: A MATLAB and Simulink-based ProductAugust 9-10, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 2August 15-16, 2023Live E-LearningConfirmed
Designing with the Versal ACAP: Power and Board DesignAugust 17, 2023Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing ClosureAugust 22-24, 2023Live E-LearningConfirmed
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteAugust 22-24, 2023Live E-LearningConfirmed
BLT Exclusive: Advanced Debug Techniques for Hardware EngineersAugust 29, 2023Live E-LearningConfirmed
BLT Exclusive: Xilinx for ManagersSeptember 5, 2023Live E-LearningConfirmed
Designing with Versal AI Engine 3: Kernel Programming and OptimizationSeptember 6-7, 2023Live E-LearningConfirmed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCSeptember 12-14, 2023Live E-LearningConfirmed
Designing with the Zynq® UltraScale+™ RFSoCSeptember 19-20, 2023Live E-LearningConfirmed
Embedded Design with PetaLinux ToolsSeptember 26-27, 2023Live E-LearningConfirmed

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

All in all a great experience.

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3