Check out the latest AMD classes on the BLT Training Calendar

We provide a range of courses including hands-on labs, interactive discussions & best practices to leverage your success. We offer online and in-person training, as well as private training. Our BLT training center is located in Columbia, MD. Class location is noted on the calendar.

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AMD Xilinx Authorized Training Provider

COURSE SCHEDULE

Note: Additional courses are available only as private classes. Please see the Course Index for the complete list.

COURSECLASS DATELOCATIONSTATUS
See All On-Demand WebinarsOn-DemandRecordedView
WEBINAR: Demystifying Clock Domain Crossings (CDC) and Synchronization CircuitsMarch 27, 2024 @ 2 PM ETOnlineVideo coming soon
WEBINAR: Versal AI Engine Tool Flow Explained: Enhancing Your Development JourneyRecordedOn-DemandWATCH
Designing with the Zynq UltraScale+ RFSoCMay 14-16, 2024Live E-Learning7 seats left

Design Closure Techniques

May 21-22, 2024Live E-Learning5 seats left
WORKSHOP: Versal Adaptive SOC: Network on Chip WorkshopMay 22, 2024 @ 10 AM ETOnlineLIMITED SEATS
WEBINAR: What is the AI Engine?May 29, 2024 @ 2 PM ETOnlineLIMITED SEATS
Designing FPGAs Using the Vivado Design Suite 4June 4-6, 2024Live E-Learning9 seats left
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCJune 11-13, 2024Live E-Learning4 seats left
WORKSHOP: Adaptive Computing for Managers: Techniques for Managing FPGA, SOC and SOM Projects (Sponsored by AMD)June 25, 2024 @ 10 AM ETOnlineVERY LIMITED SEATS
Designing FPGAs Using the Vivado Design Suite 1 - FPGA EssentialsJune 25-27, 2024Live E-Learning8 seats left
WEBINAR: Maximizing Your Debug with System ILAsJune 26, 2024 @ 2 PM ETOnlineLIMITED SEATS

Designing with the Versal Adaptive SoC: Architecture

July 16-18, 2024Live E-LearningConfirmed

Ultrafast Design Methodology

July 23-25, 2024Live E-LearningConfirmed
WORKSHOP: Unlocking AMD Embedded Software Essentials: Key Strategies & TechniquesJuly 24, 2024 @ 10 AM ETOnlineLIMITED SEATS

Embedded Design with Petalinux Tools

July 30-August 1, 2024Live E-Learning9 seats left
WEBINAR: What is AMD AI Inference? Optimizing Model Deployment for Real-World ApplicationsJuly 31, 2024 @ 2 PM ETOnlineLIMITED SEATS
Designing with VHDLAugust 13-15, 2024Live E-LearningConfirmed
Designing with Versal AI Engine: Architecture and Design Flow -1August 13-15, 2024Live E-LearningConfirmed
WORKSHOP: Versal Adaptive SoC Design Methodologies (Versal Design for Beginners)August 21, 2024 @ 10 AM ETOnlineLIMITED SEATS

High-Level Synthesis with the Vitis HLS Tool

August 27-29, 2024Live E-LearningConfirmed
WEBINAR: Increasing Design Performance Using Report QoRAugust 28, 2024 @ 2 PM ETOnlineLIMITED SEATS
Designing FPGAs Using the Vivado Design Suite 1 - FPGA EssentialsSeptember 10-12, 2024Live E-Learning9 seats left
Vitis Model Composer: A MATLAB and Simulink-based Product (DSP)September 17-19, 2024Live E-LearningConfirmed
WORKSHOP: Vitis IDE Quick StartSeptember 18, 2024 @ 10 AM ETOnlineLIMITED SEATS
BLT Exclusive: Designing and Verification with SystemVerilogSeptember 24-27, 2024Live E-LearningConfirmed
WEBINAR: Advanced RFSoC Analysis with AMD: Leveraging the RF Analyzer Tool for In-Depth InsightsSeptember 25, 2024 @ 2 PM ETOnlineLIMITED SEATS
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2October 1-3, 2024Live E-LearningConfirmed
Designing FPGAs Using the Vivado Design Suite 2– Clocking, IO, IP IntegratorOctober 8-10, 2024Live E-LearningConfirmed

BLT Exclusive: Designing an Integrated PCI Express System (Versal / UltraScale)

October 15-17, 2024Live E-LearningConfirmed
WORKSHOP: Advanced DebuggingOctober 23, 2024 @ 10 AM ETOnlineLIMITED SEATS

Design Closure Techniques

October 29-30, 2024Live E-LearningConfirmed
Designing with the Versal Adaptive SoC: Network on ChipOctober 31, 2024Live E-LearningConfirmed
Designing FPGAs Using the Vivado Design Suite 3November 5-7, 2024Live E-LearningConfirmed
Designing with Versal AI Engine: Kernel Programming and Optimization - 3November 5-7, 2024Live E-LearningConfirmed
Designing with the Zynq UltraScale+ RFSoCNovember 12-14, 2024Live E-LearningConfirmed
WORKSHOP: Digital Logic 101November 20, 2024 @ 10 AM ETOnlineLIMITED SEATS
BLT Exclusive: Designing with VerilogNovember 26-28, 2024Live E-LearningConfirmed
Designing with VHDLDecember 3-5, 2024Live E-LearningConfirmed
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteDecember 3-5, 2024Live E-LearningConfirmed
Designing FPGAs Using the Vivado Design Suite 4 – Timing Closure, Floorplanning, Debugging and TclDecember 10-12, 2024Live E-LearningConfirmed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCJanuary 22-24, 2025Live E-LearningConfirmed
Operating Systems and Hypervisors in Adaptive SoCs (formerly called ACAPs)Contact usLive E-LearningContact us
DSP Design Using System GeneratorContact usLive E-LearningContact us

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization