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Below is the current course calendar being offered by BLT Training.

Please note: All our training classes are currently offered online only. However, we look forward to in-person training in our new state-of-the-art facility when it is safe to resume in-person learning.

Our BLT training center is located in Columbia, MD. We also offer in-person training at various facilities in our training region, as well as private/custom classes. Class location will be noted on the course calendar.

COURSE SCHEDULE

COURSECLASS DATELOCATIONSTATUS
ON DEMAND: Xilinx for Managers WebinarOn-DemandRecordedWatch
ON DEMAND: Accelerating AI with the Vitis Unified Software Platform WebinarOn-DemandRecordedWatch
Webinar: Debugging Using Cross Triggering11/18/21 @ 1pm ETOnlineWatch
C-based Design: High-Level Synthesis with the Vivado HLx ToolNovember 2-3, 2021Live E-LearningConfirmed
BLT Exclusive: Designing and Verification with SystemVerilogNovember 9-11, 2021Live E-LearningConfirmed
Designing with the Versal ACAP: Network on ChipNovember 9, 2021Live E-LearningConfirmed
Designing with Versal AI Engine 1November 10-11, 2021Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingNovember 16-18, 2021Live E-LearningConfirmed
BLT Exclusive: Spartan-6 / ISE User Migration TrainingNovember 16-18, 2021Live E-LearningConfirmed
BLT Exclusive: Essential DSP Design Techniques Using System GeneratorNovember 30, 2021 - December 2, 2021Live E-LearningConfirmed
BLT Exclusive: Designing an Integrated PCI Express System with Xilinx Serial TransceiversNovember 30, 2021 - December 2, 2021Live E-LearningConfirmed
Designing with Versal AI Engine 2December 7-8, 2021Live E-LearningConfirmed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCDecember 7-9, 2021Live E-LearningConfirmed
Designing with the Versal ACAP: Power and Board DesignDecember 9, 2021Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing ClosureDecember 14-16, 2021Live E-LearningConfirmed
Designing with VHDLDecember 14-16, 2021Live E-LearningConfirmed
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteJanuary 11-12, 2022Live E-LearningConfirmed
BLT Exclusive: Advanced Debug Techniques for Hardware EngineersJanuary 13, 2022Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials - Architecture, Memory and IOJanuary 18-20, 2022Live E-LearningConfirmed
BLT Exclusive: Xilinx for ManagersJanuary 18, 2022Live E-LearningConfirmed
Designing with Versal AI Engine 3January 19-20, 2022Live E-LearningConfirmed
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoCJanuary 25-27, 2022Live E-LearningConfirmed
Designing with the Zynq UltraScale+ RFSoCFebruary 1-2, 2022Live E-LearningConfirmed
Embedded Design with PetaLinux ToolsFebruary 8-9, 2022Live E-LearningConfirmed
Designing with VHDLFebruary 15-17, 2022Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingFebruary 15-17, 2022Live E-LearningConfirmed
BLT Exclusive: Spartan-6 / ISE User Migration TrainingFebruary 15-17, 2022Live E-LearningConfirmed
Designing with VerilogFebruary 22-24, 2022Live E-LearningConfirmed
Designing with the Versal ACAP: Architecture and MethodologyMarch 1-3, 2022Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials - Architecture, Memory and IOMarch 8-10, 2022Live E-LearningConfirmed
BLT Exclusive: Designing and Verification with SystemVerilogMarch 15-17, 2022Live E-LearningConfirmed
C-based Design: High-Level Synthesis with the Vivado HLx ToolMarch 15-16, 2022Live E-LearningConfirmed
Designing with the Versal ACAP: Network on ChipMarch 22, 2022Live E-LearningConfirmed
Designing with Versal AI Engine 1March 23-24, 2022Live E-LearningConfirmed
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and DebuggingMarch 29-31, 2022Live E-LearningConfirmed
BLT Exclusive: Essential DSP Design Techniques Using System GeneratorApril 5-7, 2022Live E-LearningConfirmed
BLT Exclusive: Designing an Integrated PCI Express System with Xilinx Serial TransceiversApril 5-7, 2022Live E-LearningConfirmed
Designing with Versal AI Engine 2April 12-13, 2022Live E-LearningConfirmed
Designing with the Versal ACAP: Power and Board DesignApril 14, 2022Live E-LearningConfirmed

Training Courses

BLT provides a broad range of courses including hands-on labs, interactive discussions and best practices designed to leverage your success.

For Questions Contact

888-XILINX-1
[email protected]