Course Calendar
We provide a range of courses including hands-on labs, interactive discussions & best practices to leverage your success. We offer online and in-person training, as well as private training. Our BLT training center is located in Columbia, MD. Class location is noted on the calendar.
Not sure where to start? Check out our Learning Path.
View the calendar below or find a class another way:
COURSE SCHEDULE
COURSE | CLASS DATE | LOCATION | STATUS |
---|---|---|---|
See All On-Demand Webinars | On-Demand | Recorded | View |
Webinar: Introduction to AXI / AXI Verification IP | November 1, 2023 | Live E-Learning | Recording coming soon |
Webinar: Space Application RFSoCs / State Machines | November 15, 2023 | Live E-Learning | Recording coming soon |
Webinar: Getting Started with the Kria SOM | November 29, 2023 @ 2 PM ET | Live E-Learning | Recording coming soon |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure | December 12-14, 2023 | Live E-Learning | 2 seats left |
Live E-Learning | Contact us | ||
BLT Exclusive: Advanced Debugging Workshop (Sponsored by AMD Xilinx) | December 13, 2023 | Live E-Learning | LIMITED SEATS |
January 23-24, 2024 | Live E-Learning | Closed | |
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC | January 23-25, 2024 | Live E-Learning | 6 seats left |
Embedded Design with PetaLinux Tools | January 30-31, 2024 | Live E-Learning | Confirmed |
Webinar: Closing Timing Using Intelligent Design Flow (Spotlight: AMD New Tool Feature) | January 31, 2024 @ 2 PM ET | Live E-Learning | LIMITED SEATS |
Designing with the Versal ACAP: Network on Chip | February 6, 2024 | Live E-Learning | Confirmed |
Designing with Versal AI Engine 1: Architecture and Design Flow | February 7-8, 2024 | Live E-Learning | Confirmed |
Designing with VHDL | February 13-15, 2024 | Live E-Learning | 8 seats left |
Designing with Verilog | February 20-22, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Implementing DSP Using Vitis Model Composer Workshop (sponsored by AMD Xilinx) | February 21, 2024 @ 10 AM ET | Online | LIMITED SEATS |
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | February 27-28, 2024 | Live E-Learning | Confirmed |
WEBINAR: Debug Techniques for Vivado Block Designs | February 28, 2024 @ 2 PM ET | Online | LIMITED SEATS |
Designing FPGAs Using the Vivado Design Suite 1 | March 5-6, 2024 | Live E-Learning | Contact us |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO | March 5-7, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Designing and Verification with SystemVerilog | March 12-14, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Mastering Vivado Timing Constraints: Strategies for FPGA Performance | March 20, 2024 @ 10 AM ET | Online | LIMITED SEATS |
Designing with Versal AI Engine 3: Kernel Programming and Optimization | March 19-20, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging | March 26-28, 2024 | Live E-Learning | 7 seats left |
WEBINAR: Demystifying Clock Domain Crossings (CDC) and Synchronization Circuits | March 27, 2024 @ 2 PM ET | Online | LIMITED SEATS |
Designing FPGAs Using the Vivado Design Suite 2 | March 26-27, 2024 | Live E-Learning | Contact us |
Designing with the Zynq UltraScale+ RFSoC | April 9-11, 2024 | Live E-Learning | Confirmed |
April 16-17, 2024 | Live E-Learning | Contact us | |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure | April 16-18, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Adaptive SoCs 101: Quick Start Guide to Integration and Implementation | April 23, 2024 @ 10 AM ET | Online | LIMITED SEATS |
April 23-24, 2024 | Live E-Learning | Confirmed | |
Dynamic Function eXchange (DFX) Using the Vivado Design Suite | April 30 - May 1, 2024 | Live E-Learning | Confirmed |
WEBINAR: Versal AI Engine Tool Flow Explained: Enhancing Your Development Journey | May 1, 2024 @ 2 PM ET | Online | LIMITED SEATS |
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC | May 5-7, 2024 | Live E-Learning | Confirmed |
Operating Systems and Hypervisors in Adaptive SoCs (formerly called ACAPs) | May 7, 2024 | Live E-Learning | Contact us |
Embedded Design with PetaLinux Tools | May 14-15, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Designing an Integrated PCI Express System (Versal / UltraScale) | May 21-22, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Versal Adaptive SOC: Network on Chip Workshop | May 22, 2024 @ 10 AM ET | Online | LIMITED SEATS |
WEBINAR: What is the AI Engine? | May 29, 2024 @ 2 PM ET | Online | LIMITED SEATS |
Designing with VHDL | June 4-6, 2024 | Live E-Learning | Confirmed |
Designing with Verilog | June 11-13, 2024 | Live E-Learning | Confirmed |
Vitis Model Composer: A MATLAB and Simulink-based Product (DSP) | June 18-20, 2024 | Live E-Learning | 9 seats left |
DSP Design Using System Generator | June 18-19, 2024 | Live E-Learning | Contact us |
WORKSHOP: Adaptive Computing for Managers | June 19, 2024 @ 10 AM ET | Online | LIMITED 25 SEATS |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO | June 25-27, 2024 | Live E-Learning | Confirmed |
Designing FPGAs Using the Vivado Design Suite 1 | June 25-26, 2024 | Live E-Learning | Contact us |
WEBINAR: Maximizing Your Debug with System ILAs | June 26, 2024 @ 2 PM ET | Online | LIMITED SEATS |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging | July 16-18, 2024 | Live E-Learning | Confirmed |
Designing FPGAs Using the Vivado Design Suite 2 | July 16-17, 2024 | Live E-Learning | Contact us |
BLT Exclusive: Designing and Verification with SystemVerilog | July 23-25, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Unlocking AMD Embedded Software Essentials: Key Strategies & Techniques | July 24, 2024 @ 10 AM ET | Online | LIMITED SEATS |
Designing with the Versal ACAP: Network on Chip | July 30, 2024 | Live E-Learning | Confirmed |
WEBINAR: What is AMD AI Inference? Optimizing Model Deployment for Real-World Applications | July 31, 2024 @ 2 PM ET | Online | LIMITED SEATS |
Designing with Versal AI Engine 1: Architecture and Design Flow | July 31 - August 1, 2024 | Live E-Learning | Confirmed |
August 6-7, 2024 | Live E-Learning | Contact us | |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure | August 6-8, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Advanced Debugging | August 21, 2024 @ 10 AM ET | Online | LIMITED SEATS |
Designing with the Versal ACAP: Architecture and Methodology | August 20-22, 2024 | Live E-Learning | Confirmed |
UltraFast Design Methodology | August 27-28, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC | August 27-29, 2024 | Live E-Learning | Confirmed |
WEBINAR: Increasing Design Performance Using Report QoR | August 28, 2024 @ 2 PM ET | Online | LIMITED SEATS |
September 3-4, 2024 | Live E-Learning | Confirmed | |
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | September 10-11, 2024 | Live E-Learning | Confirmed |
Designing with VHDL | September 17-19, 2024 | Live E-Learning | Confirmed |
WORKSHOP: Digital Logic 101 | September 18, 2024 @ 10 AM ET | Online | LIMITED SEATS |
Embedded Design with PetaLinux Tools | September 24-25, 2024 | Live E-Learning | Confirmed |
WEBINAR: Advanced RFSoC Analysis with AMD: Leveraging the RF Analyzer Tool for In-Depth Insights | September 25, 2024 @ 2 PM ET | Online | LIMITED SEATS |
Designing with Versal AI Engine 3: Kernel Programming and Optimization | October 1-2, 2024 | Live E-Learning | Confirmed |
Designing with Verilog | October 15-17, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO | October 8-10, 2024 | Live E-Learning | Confirmed |
Designing FPGAs Using the Vivado Design Suite 1 | October 8-9, 2024 | Live E-Learning | Contact us |
Designing with the Zynq UltraScale+ RFSoC | October 22-24, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging | October 29-31, 2024 | Live E-Learning | Confirmed |
Designing FPGAs Using the Vivado Design Suite 2 | October 29-30, 2024 | Live E-Learning | Contact us |
BLT Exclusive: Designing and Verification with SystemVerilog | November 5-7, 2024 | Live E-Learning | Confirmed |
Dynamic Function eXchange (DFX) Using the Vivado Design Suite | November 12-14, 2024 | Live E-Learning | Confirmed |
November 26-27, 2024 | Live E-Learning | Contact us | |
BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure | November 26-28, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Designing an Integrated PCI Express System (Versal / UltraScale) | December 3-4, 2024 | Live E-Learning | Confirmed |
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC | December 10-12, 2024 | Live E-Learning | Confirmed |
Thanks for a great class!
I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!
– Student from Vivado Boot Camp for the FPGA User Phase 1
This one was definitely one of the best
I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!
– Student from Vivado Boot Camp for the FPGA User Phase 1
Labs were great
The labs were great and really reinforced the topics.
– Student from Designing with Versal AI Engine 1: Architecture and Design Flow
The instructor was excellent
The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.
– Student from Embedded Design with PetaLinux Tools
Elie was an exceptional instructor
Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.
– Student from Designing with Verilog
My instructor was very capable
My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question
– Student from Vivado Boot Camp for the FPGA User Phase 1
Impressed with the effort
Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.
– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization
All in all a great experience
Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.
– Student from Vivado Boot Camp for the FPGA User Phase 2
Knowledgeable instructor
Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.
– Student from Designing with VHDL
I gained a lot of information
The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!
– Student from Vivado Boot Camp for the FPGA User Phase 1
Can quickly and concisely answer technical questions
I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!
– Student from Vivado Boot Camp for the FPGA User Phase 3
One of the best experiences for AMD Xilinx training that I’ve had
Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.
– Student from Designing with VHDL
My instructor took time
My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.
– Student from Vivado Boot Camp for the FPGA User Phase 3
My instructor was very professional
My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.
– Student from Vivado Boot Camp for the FPGA User Phase 1
Erich was engaging
Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.
– Student from Vivado Boot Camp for the FPGA User Phase 1
College course fit into 3 days
The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.
– Student from Designing with VDHL
They had answers for just about every question
Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.
– Student from Vivado Boot Camp for the FPGA User Phase 2
I would endorse him to teach a friend
Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.
– Student from Designing with Verilog
Expert tidbits
I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.
– Student from Designing with VHDL
I had a wonderful instructor
I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.
– Student from Vivado Boot Camp for the FPGA User Phase 3
A lot of insights beyond the course
Glenn was a great instructor and provided us with a lot of insights beyond the course material
– Student from Embedded Design with PetaLinux Tools