How to Design a High-Speed Memory Interface

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

Please contact the BLT Training Team to schedule a private class.

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.

Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.

The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex-7 FPGA KC705 board.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the FPGA resources required for memory interfaces
  • Describe different types of memories
  • Utilize Xilinx tools to generate memory interface designs
  • Simulate memory interfaces with the Xilinx Vivado simulator
  • Implement memory interfaces
  • Identify the board design options for the realization of memory interfaces
  • Test and debug your memory interface design
  • Run basic memory interface signal integrity simulations

Course Outline

Day 1

  • Course Introduction
  • 7 Series FPGAs Overview
  • Memory Devices Overview
  • 7 Series Memory Interface Resources
  • Memory Controller Details and Signals
  • MIG Design Generation
  • LAB: MIG Core Generation
    Create a DDR3 memory controller using the Memory Interface Generator (MIG) in the Vivado IP catalog. Customize the soft core memory controller for the board.
  • MIG Design Simulation
  • LAB: MIG Design Simulation
    Simulate the memory controller created in Lab 1 using the Vivado simulator or Mentor Graphics QuestaSim simulator.

Day 2

  • MIG Design Implementation
  • LAB: MIG Design Implementation
    Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.
  • Memory Interface Test and Debugging
  • LAB: MIG Design Debugging
    Debug the memory interface design utilizing the Vivado logic analzyer.
  • MIG in Embedded Designs
  • LAB: MIG in IP Integrator
    Use the block design editor to include the MIG IP in a given processor design.
  • Memory Interface Board-Level Design
  • DDR3 PCB Simulation (optional)
  • LAB: DDR3 Signal Integrity Simulation (optional)
    Learn basic signal analysis options to check waveforms and design optimization.


Training Duration:

2 Days

Who should attend:

FPGA designers and logic designers


  • VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
  • Familiarity with logic design, state machines and synchronous design
  • Very helpful to have: Basic knowledge of FPGA architecture
  • Familiarity with Xilinx implementation tools
  • Nice to have: Familiarity with I/O basics and high-speed I/O standards

Version: 2021-03-17_0932