How to Design a High-Speed Memory Interface

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs. Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces. The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex-7 FPGA KC705 board.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the FPGA resources required for memory interfaces
  • Describe different types of memories
  • Utilize Xilinx tools to generate memory interface designs
  • Simulate memory interfaces with the Xilinx Vivado simulator
  • Implement memory interfaces
  • Identify the board design options for the realization of memory interfaces
  • Test and debug your memory interface design
  • Run basic memory interface signal integrity simulations

Course Outline

Day 1

  • Course Introduction
  • 7 Series FPGAs Overview
  • Memory Devices Overview
  • 7 Series Memory Interface Resources
  • Memory Controller Details and Signals
  • MIG Design Generation
  • Lab 1: MIG Core GenerationCreate a DDR3 memory controller using the Memory Interface Generator (MIG) in the Vivado IP catalog. Customize the soft core memory controller for the board.
  • MIG Design Simulation
  • Lab 2: MIG Design SimulationSimulate the memory controller created in Lab 1 using the Vivado simulator or Mentor Graphics QuestaSim simulator.

Day 2

  • MIG Design Implementation
  • Lab 3: MIG Design ImplementationImplement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.
  • Memory Interface Test and Debugging
  • Lab 4: MIG Design DebuggingDebug the memory interface design utilizing the Vivado logic analzyer.
  • MIG in Embedded Designs
  • Lab 5: MIG in IP IntegratorUse the block design editor to include the MIG IP in a given processor design.
  • Memory Interface Board-Level Design
  • DDR3 PCB Simulation (optional)
  • Lab 6: DDR3 Signal Integrity Simulation (optional)Learn basic signal analysis options to check waveforms and design optimization.

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

FPGA designers and logic designers

Prerequisites

VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course

Familiarity with logic design: state machines and synchronous design

Very helpful to have:Basic knowledge of FPGA architecture

Familiarity with Xilinx implementation tools

Nice to have:Familiarity with I/O basicsFamiliarity with high-speed I/O standard

Software Tools

Vivado Design or System Edition 2015.1Mentor Graphics QuestaSim Advanced Simulator 10.3dMentor Graphics HyperLynx SI 9.x

Hardware

Architecture: 7 series FPGAs*Demo board: Kintex-7 FPGA KC705 board** This course focuses on the 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626