DSP Design Using System Generator
DSP Design Using System Generator
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the System Generator design flow for implementing DSP functions
- Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
- List various low-level and high-level functional blocks available in System Generator
- Run hardware co-simulationIdentify the high-level blocks available for FIR and FFT designs
- Implement multi-rate systems in System Generator
- Integrate System Generator models into the Vivado™ IDE
- Design a processor-controllable interface using System Generator for DSP
- Generate IPs from C-based design sources for use in the System Generator environment
Course Outline
Day 1
- Introduction to System Generator
- Simulink Software Basics
- Lab 1: Using the Simulink SoftwareLearn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
- Basic Xilinx Design Capture
- Demo: System Generator Gateway Blocks
- Lab 2: Getting Started with Xilinx System GeneratorIllustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
- Signal Routing
- Lab 3: Signal RoutingDesign padding and unpadding logic by using signal routing blocks.
- Implementing System Control
- Lab 4: Implementing System ControlDesign an address generator circuit by using blocks and Mcode.
Day 2
- Multi-Rate Systems
- Lab 5: Designing a MAC-Based FIRUsing a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
- Filter Design
- Lab 6: Designing a FIR Filter Using the FIR Compiler BlockDesign a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
- System Generator, Vivado™ Design Suite, and Vivado™ HLS Integration
- Lab 7: System Generator and Vivado™ IDE IntegrationEmbed System Generator models into the Vivado™ IDE.
- Kintex-7 FPGA DSP Platforms
- Lab 8: System Generator and Vivado™ HLS Tool IntegrationGenerate IP from a C-based design to use with System Generator.
- Lab 9: AXI4-Lite Interface SynthesisPackage a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq® All Programmable SoC processor syst
Scheduled Classes
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Training Duration:
2 Days
Who should attend:
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB and Simulink software and want to use Xilinx System Generator for DSP design.
Prerequisites
Experience with the MATLAB and Simulink softwareBasic understanding of sampling theory
Software Tools
Vivado™ System Edition 2016.3MATLAB with Simulink software R2016b
Hardware
Architecture: 7 series and Ultrascale™ FPGAs*Demo board: Kintex-7 FPGA KC705 board or Kintex UltraSale FPGA KCU105 board and Zynq®-7000 All Programmable SoC ZC702 or ZedBoard** Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. The ZC702 or ZedBoard is required for the "AXI4-Lite Interface Synthesis" lab.