DSP Design Using System Generator

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the System Generator design flow for implementing DSP functions
Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
List various low-level and high-level functional blocks available in System Generator
Run hardware co-simulation
Identify the high-level blocks available for FIR and FFT designs
Implement multi-rate systems in System Generator
Integrate System Generator models into the Vivado^™ IDE
Design a processor-controllable interface using System Generator for DSP
Generate IPs from C-based design sources for use in the System Generator environment

Course Outline

Day 1 Day 2

Day 1

Introduction to System Generator
Simulink Software Basics
LAB: Using the Simulink Software
Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
Basic Xilinx Design Capture
Demo: System Generator Gateway Blocks
LAB: Getting Started with Xilinx System Generator
Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
Signal Routing
LAB: Signal Routing
Design padding and unpadding logic by using signal routing blocks.
Implementing System Control
LAB: Implementing System Control
Design an address generator circuit by using blocks and Mcode.

Day 2

Multi-Rate Systems
LAB: Designing a MAC-Based FIR
Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
Filter Design
LAB: Designing a FIR Filter Using the FIR Compiler Block
Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
System Generator, Vivado^™ Design Suite, and Vivado^™ HLS Integration
LAB: System Generator and Vivado^™ IDE Integration
Embed System Generator models into the Vivado^™ IDE.
Kintex-7 FPGA DSP Platforms
LAB: System Generator and Vivado^™ HLS Tool Integration
Generate IP from a C-based design to use with System Generator.
LAB: AXI4-Lite Interface Synthesis
Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq^® All Programmable SoC processor system.

Scheduled Classes

Columbia, MD

5/6/2020 – 5/7/2020

Sterling, Virginia

5/13/2020 – 5/14/2020

Sterling, Virginia

8/12/2020 – 8/13/2020

Columbia, MD

8/19/2020 – 8/20/2020

Education Investment Options

Standard Registration

$2,000

Standard Registration

20 Training Credits

Advanced Registration

$1,800

Advanced Registration

18 Training Credits

Basic Follow-on Coaching

$500

Comprehensive Follow-on Coaching

$2,500

To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
Basic follow-on coaching includes 2 hours (max 2 calls)
Comprehensive follow-on coaching includes 10 hours (max 5 calls)
Follow-on Coaching must be purchased at time of registration.

To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB and Simulink software and want to use Xilinx System Generator for DSP design.

Prerequisites:

Experience with the MATLAB and Simulink software
Basic understanding of sampling theory

Version: 2020-02-28_1026