$299/Day - DSP Design Using System Generator - BLT Training

DSP Design Using System Generator

BLT offers a newer course for this material: Essential DSP Design Techniques Using System Generator

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost digital signal processing (DSP) designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.

Learn more about Xilinx digital signal processing (DSP) applications here.

For more about the Xilinx System Generator for DSP, click here.

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (mailed to you)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions – Contact Us to ask about setting one up!

Training Duration:

2 Days

We update our schedule regularly. Stay informed.

NEWSLETTER SIGNUP

Who should attend:

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB and Simulink software and want to use Xilinx System Generator for DSP design.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the System Generator design flow for implementing digital signal processing (DSP) functions
Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
List various low-level and high-level functional blocks available in System Generator
Run hardware co-simulation
Identify the high-level blocks available for FIR and FFT designs
Implement multi-rate systems in System Generator
Integrate System Generator models into the Xilinx Vivado^™ IDE
Design a processor-controllable interface using System Generator for DSP
Generate IPs from C-based design sources for use in the System Generator environment

Course Outline

Day 1	Day 2
Introduction to System Generator Simulink Software Basics LAB: Using the Simulink Software Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate. Basic Xilinx Design Capture Demo: System Generator Gateway Blocks LAB: Getting Started with Xilinx System Generator Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board. Signal Routing LAB: Signal Routing Design padding and unpadding logic by using signal routing blocks. Implementing System Control LAB: Implementing System Control Design an address generator circuit by using blocks and Mcode.	Multi-Rate Systems LAB: Designing a MAC-Based FIR Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board. Filter Design LAB: Designing a FIR Filter Using the FIR Compiler Block Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board. System Generator, Vivado^™ Design Suite, and Vivado^™ HLS Integration LAB: System Generator and Vivado^™ IDE Integration Embed System Generator models into the Vivado^™ IDE. Kintex-7 FPGA DSP Platforms LAB: System Generator and Vivado^™ HLS Tool Integration Generate IP from a C-based design to use with System Generator. LAB: AXI4-Lite Interface Synthesis Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq^® All Programmable SoC processor system.

Day 1

Day 2

Introduction to System Generator
Simulink Software Basics
LAB: Using the Simulink Software
Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
Basic Xilinx Design Capture
Demo: System Generator Gateway Blocks
LAB: Getting Started with Xilinx System Generator
Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
Signal Routing
LAB: Signal Routing
Design padding and unpadding logic by using signal routing blocks.
Implementing System Control
LAB: Implementing System Control
Design an address generator circuit by using blocks and Mcode.

Multi-Rate Systems
LAB: Designing a MAC-Based FIR
Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
Filter Design
LAB: Designing a FIR Filter Using the FIR Compiler Block
Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
System Generator, Vivado^™ Design Suite, and Vivado^™ HLS Integration
LAB: System Generator and Vivado^™ IDE Integration
Embed System Generator models into the Vivado^™ IDE.
Kintex-7 FPGA DSP Platforms
LAB: System Generator and Vivado^™ HLS Tool Integration
Generate IP from a C-based design to use with System Generator.
LAB: AXI4-Lite Interface Synthesis
Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq^® All Programmable SoC processor system.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Experience with the MATLAB and Simulink software
Basic understanding of sampling theory

DSP Design Using System Generator

DSP Design Using System Generator

Scheduled Classes

Training Duration:

We update our schedule regularly. Stay informed.

Who should attend:

Skills Gained

Course Outline

Prerequisites:

Related Courses:

Updated 9-02-2021