$299/Day - Designing with UltraScale FPGA Transceivers

Designing with UltraScale FPGA Transceivers

Learn how to employ serial transceivers in your UltraScale^™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.

Learn more about UltraScale from Xilinx®.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

Be the first to know. Sign up for our newsletter.

Who should attend:

FPGA designers and logic designers

Skills Gained

After completing this comprehensive training, you will know how to:

Describe and utilize the ports and attributes of the serial transceiver in UltraScale FPGAs
Effectively utilize the following features of the gigabit transceivers:64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding, Pre-emphasis and receive equalization
Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
Use the IBERT design to verify transceiver links on real hardware

Course Outline

Day 1	Day 2
UltraScale FPGA Overview UltraScale FPGA Transceivers Overview UltraScale FPGAs Transceivers Clocking and Resets Transceiver Wizard Overview LAB: Transceiver Core Generation Use the UltraScale FPGAs Transceivers Wizard to create instantiation templates. Transceiver Simulation LAB: Transceiver Simulation Simulate the transceiver IP by using the IP example design. PCS Layer General Functionality	PCS Layer Encoding LAB: 64B/66B Encoding Generate a 64B/66B transceiver core by using the UltraScale FPGAs Transceivers Wizard, simulate the design, and analyze the results. Transceiver Implementation LAB: Transceiver Implementation Implement the transceiver IP by using the IP example design. PMA Layer Details Transceiver Board Design Considerations Transceiver Test and Debugging LAB: IBERT Design Verify transceiver links on real hardware. Transceiver Application Examples

Day 1

Day 2

UltraScale FPGA Overview
UltraScale FPGA Transceivers Overview
UltraScale FPGAs Transceivers Clocking and Resets
Transceiver Wizard Overview
LAB: Transceiver Core Generation
Use the UltraScale FPGAs Transceivers Wizard to create instantiation templates.
Transceiver Simulation
LAB: Transceiver Simulation
Simulate the transceiver IP by using the IP example design.
PCS Layer General Functionality

PCS Layer Encoding
LAB: 64B/66B Encoding
Generate a 64B/66B transceiver core by using the UltraScale FPGAs Transceivers Wizard, simulate the design, and analyze the results.
Transceiver Implementation
LAB: Transceiver Implementation
Implement the transceiver IP by using the IP example design.
PMA Layer Details
Transceiver Board Design Considerations
Transceiver Test and Debugging
LAB: IBERT Design
Verify transceiver links on real hardware.
Transceiver Application Examples

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
Familiarity with logic design (state machines and synchronous design)
Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

RELATED COURSES:

Updated 7-14-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.