Designing with UltraScale™ FPGA Transceivers
Designing with UltraScale™ FPGA Transceivers
Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale™ FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe and utilize the ports and attributes of the serial transceiver in UltraScale™ FPGAs
- Effectively utilize the following features of the gigabit transceivers:64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding, Pre-emphasis and receive equalization
- Use the UltraScale™ FPGAs Transceivers Wizard to instantiate GT primitives in a design
- Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
- Use the IBERT design to verify transceiver links on real hardware
Course Outline
Day 1
- UltraScale™ FPGA Overview
- UltraScale™ FPGA Transceivers Overview
- UltraScale™ FPGAs Transceivers Clocking and Resets
- Transceiver Wizard Overview
- LAB: Transceiver Core Generation
Use the UltraScale™ FPGAs Transceivers Wizard to create instantiation templates. - Transceiver Simulation
- LAB: Transceiver Simulation
Simulate the transceiver IP by using the IP example design. - PCS Layer General Functionality
Day 2
- PCS Layer Encoding
- LAB: 64B/66B Encoding
Generate a 64B/66B transceiver core by using the UltraScale™ FPGAs Transceivers Wizard, simulate the design, and analyze the results. - Transceiver Implementation
- LAB: Transceiver Implementation
Implement the transceiver IP by using the IP example design. - PMA Layer Details
- Transceiver Board Design Considerations
- Transceiver Test and Debugging
- LAB: IBERT Design
Verify transceiver links on real hardware. - Transceiver Application Examples
No Scheduled Sessions – Contact Us to ask about setting one up!
Education Investment Options
Standard Registration
$2,000
Standard Registration
20 Training Credits
Advanced Registration
$1,800
Advanced Registration
18 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
REGISTER
Training Duration:
2 Days
Who should attend:
FPGA designers and logic designers
Prerequisites:
- Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Version: 2021-03-17_0932