Designing with the Spartan-6 and Virtex-6 FPGA Families

Are you interested in learning how to effectively utilize Spartan-6 or Virtex-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Vivado Boot Camp: Basic Training course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.

Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express technology, and GTP transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.Note: A two-day Spartan-6 family only course or two-day Virtex-6 family only course is also available.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 and Virtex-6 FPGAs
  • Specify the CLB resources and the available slice configurations for the Spartan-6 and Virtex-6 FPGAs
  • Define the block RAM and DSP resources available for Spartan-6 and Virtex-6 FPGAs
  • Properly design for the I/O block and SERDES resources
  • Identify the DCM, PLL, and clock routing resources included with each of these families
  • Identify the supported memory controllers for the Spartan-6 and Virtex-6 FPGAs
  • Properly code your HDL to get the most out of these devices
  • Describe the additional dedicated hardware for all the Spartan-6 and Virtex-6 families
  • Identify the features of the 7 series families

Course Outline

Full Course Outline Day 1

  • Spartan-6 FPGA Overview
  • Virtex-6 FPGA Overview
  • CLB Architecture
  • HDL Coding Techniques
  • Lab 1: CLB ResourcesUsing XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Memory Resources
  • DSP Resources

Full Course Outline Day 2

  • Lab 2: DSP ResourcesUsing XST, synthesize and implement a wide MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator® tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Basic I/O Resources
  • Spartan-6 FPGA I/O Resources
  • Virtex-6 FPGA I/O Resources
  • Lab 3: I/O ResourcesUsing the ISE tools, complete the construction of the transmit SERDES datapath. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the FPGA that are used for construction of a high-speed interface.
  • Basic Clocking Resources

Full Course Outline Day 3

  • Spartan-6 FPGA Clocking Resources
  • Virtex-6 FPGA Clocking Resources
  • Lab 4: Clocking ResourcesUsing the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.
  • Memory Controllers
  • Dedicated Hardware

Spartan-6 Family Only Course Outline Day 1

  • Spartan-6 FPGA Overview
  • CLB Architecture
  • HDL Coding Techniques
  • Lab 1: CLB ResourcesUsing XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Memory Resources
  • DSP Resources
  • Lab 2: DSP ResourcesUsing XST, synthesize and implement a wide MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator® tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Basic I/O Resources
  • Spartan-6 FPGA I/O Resources

Spartan-6 Family Only Course Outline Day 2

  • Lab 3: I/O ResourcesUsing the ISE tools, complete the construction of the transmit SERDES datapath. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the FPGA that are used for construction of a high-speed interface.
  • Basic Clocking Resources
  • Spartan-6 FPGA Clocking Resources
  • Lab 4: Clocking ResourcesUsing the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.
  • Memory Controllers
  • Dedicated Hardware

Virtex-6 Family Only Course Outline Day 1

  • Virtex-6 FPGA Overview
  • CLB Architecture
  • HDL Coding Techniques
  • Lab 1: CLB ResourcesUsing XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Memory Resources
  • DSP Resources
  • Lab 2: DSP ResourcesUsing XST, synthesize and implement a wide MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator® tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Basic I/O Resources

Virtex-6 Family Only Course Outline Day 2

  • Virtex-6 FPGA I/O Resources
  • Lab 3: I/O ResourcesUsing the ISE tools, complete the construction of the transmit SERDES datapath. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the FPGA that are used for construction of a high-speed interface.
  • Basic Clocking Resources
  • Virtex-6 FPGA Clocking Resources
  • Lab 4: Clocking ResourcesUsing the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.
  • Memory Controllers
  • Dedicated Hardware

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$2,700
Standard Registration
27 Training Credits
Advanced Registration
$2,400
Advanced Registration
24 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

3 Days

Who should attend:

For those who have taken the Vivado Boot Camp: Basic Training course

Prerequisites

Vivado Boot Camp: Basic Training course

Intermediate VHDL or Verilog knowledge

Software Tools

Xilinx ISE Design Suite: Logic or System Edition 13.1

Hardware

Artix-7, Kintex-7, and Virtex-7 FPGAsDemo board: None* This course focuses on the 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626