Embedded Heterogeneous Design 

(For Getting Started with Versal Devices)

COURSE CODE: EMBD-HET

This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project to design an embedded heterogeneous system using the v++ tools and AMD Vitis™ Unified IDE.

The emphasis of this course is on:

  • Describing an embedded heterogeneous system design
  • Illustrating the AMD Versal adaptive SoC architecture, NoC, and AI Engine
  • Describing an AMD Versal design tool flow
  • Developing HLS and AIE components using the AMD Vitis tool
  • Utilizing the v++ command line tools for component compilation, linking, and packaging to run emulation
  • Demonstrating the system design flow for a heterogeneous embedded system using the AMD Vitis Unified IDE

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

Live Online Training (9am-5pm ET)
Training Duration:

3 Days

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

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Who should attend:

Software and hardware developers, system architects, and anyone who needs to accelerate their software
applications using AMD devices.

Software Tools

  • AMD Vitis Unified IDE 2023.2

Hardware

  • Architecture: AMD Versal adaptive SoCs

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Identify the resources available in AMD adaptive SoC architectures
  • Describe the processes for developing the components for each type of resource
  • Describe the optimization and debug methodologies for each component
  • Develop components and link and package a system design using the v++ tools
  • Assemble a complete system and run hardware emulation using the AMD Vitis Unified IDE

Course Outline

Day 1Day 2Day 3
Introduction to Embedded Heterogeneous Design
Defines what an embedded heterogeneous design is and identifies the AMD SoCs that support these types of designs. Also describes the tools required to develop embedded heterogeneous designs with AMD Versal devices. {Lecture}

Versal Adaptive SoC - Architecture Overview
Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture}

Versal Adaptive SoC - NoC Architecture
Provides a deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}

Versal AI Engine Architecture
Introduces the architecture of the AI Engine and its components. {Lecture}

Versal AI Engine Memory and Data Movement
Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays. {Lecture}

Versal Adaptive SoC - Application Partitioning 1
Covers what application partitioning is and how an application can be accelerated by using the various compute domains in the Versal device. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal adaptive SoC. {Lecture}
Driving the AMD Vitis Unified IDE
Introduces the terminology and features of the Vitis Unified IDE and talks about the basic behaviors required to drive the Vitis Unified IDE to generate a C/C++ application. {Lecture}

Tool Flow for Heterogeneous Systems

Maps the various compute domains in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}

Introduction to Vitis High-Level Synthesis Components
Provides an overview of high-level synthesis (HLS), the Vitis Unified IDE for HLS development flow, and the verification advantage. {Lecture, Lab}

Vitis HLS Methodology and Optimization Techniques
Describes the different methodologies of Vitis HLS development and various optimization techniques for improving performance. {Lecture, Lab}

AI Engine Programming: Kernels and Graphs
Describes AI Engine kernels and adaptive data flow (ADF) graphs along with their programming flows. {Lecture, Lab}
Analyzing AI Engine Design Reports Using the Vitis Unified IDE
Describes the different reports generated by the tool and how to view the reports that help to optimize and debug AI Engine kernels using the Analysis view in the Vitis Unified IDE. {Lecture}

Versal AI Engine Application Debug and Trace
Shows how to debug an AI Engine application running on the Linux® OS and how to debug via hardware emulation that allows simulation of the application. {Lecture}

Development Using the v++ Command Line Tools
Illustrates the v++ command line tool flow for compiling AI Engine designs and HLS kernels and linking them for use on a target platform. Package a design to run software/hardware emulation is also covered. {Lecture, Lab}

Custom Platform Development
Describes the custom platform creation process using the AMD Vivado™ IP integrator, RTL, HLS, and Vitis environment. {Lecture, Lab}

Embedded Heterogeneous System Design Flow
Demonstrates the Vitis compiler flow to integrate a compiled AI Engine design graph (libadf.a) with additional kernels implemented in the PL region of the device (including HLS and RTL kernels) and linking them for use on a target platform. These compiled hardware functions can then be called from a host program running in the Arm® processor in the Versal device or on an external x86 processor. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Comfort with the C/C++ programming language
  • Software development flow
  • AMD Vitis tool flow

RELATED COURSES:

Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.