$299/Day - Designing with Verilog - Language Course

Designing with Verilog

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx® devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$897	9
In-Person Registration - $399/day	$1197	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

Live Online Training (9am-5pm ET)

June 13-15, 2023 | Register Today

October 10-12, 2023 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

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Who should attend:

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.

Skills Gained

After completing this comprehensive training, you will know how to:

Write RTL Verilog code for synthesis
Write Verilog test fixtures for simulation
Create a Finite State Machine (FSM) by using Verilog
Target and optimize Xilinx FPGAs by using Verilog
Use enhanced Verilog file I/O capability
Run a timing simulation by using Xilinx Simprim libraries
Create and manage designs within the Vivado® Design Suite environment
Download to the evaluation demo board

Course Outline

Day 1	Day 2	Day 3
Introduction to Verilog Verilog Keywords and Identifiers Verilog Data Values and Number Representation Verilog Data Types Verilog Buses and Arrays Verilog Modules and Ports Verilog Operators Continuous Assignment Gate-Level Modeling Procedural Assignment Blocking and Non-Blocking Procedural Assignment Procedural Timing Control	Verilog Conditional Statements: if_else Verilog Conditional Statements: case Verilog Loop Statements Introduction to Verilog Testbenches System Tasks Verilog Sub-Programs Verilog Functions Verilog Tasks Verilog Compiler Directives Verilog Parameters Verilog Generate Statement	Verilog Timing Checks Finite State Machines Mealy Finite State Machine Moore Finite State Machine FSM Coding Guidelines File I/O: Introduction File I/O: Read Functions File I/O: Write Functions Targeting Xilinx FPGAs User-Defined Primitives Programming Language Interface

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic digital design knowledge

RELATED COURSES:

Updated 3-22-2023

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