Designing with Verilog

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$8979
In-Person Registration - $399/day$119712
Printed Course Book (mailed to you)$1001
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Scheduled Classes

Live Online Training: October 12-14, 2021
Live Online Training: February 22-24, 2022

Training Duration:

3 Days

We update our schedule regularly. Stay informed.

Who should attend:

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a Finite State Machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capability
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the Vivado Design Suite environment
  • Download to the evaluation demo board

Course Outline

Day 1Day 2Day 3
  • Introduction to Verilog
  • Verilog Keywords and Identifiers
  • Verilog Data Values and Number Representation
  • Verilog Data Types
  • Verilog Buses and Arrays
  • Verilog Modules and Ports
  • Verilog Operators
  • Continuous Assignment
  • Gate-Level Modeling
  • Procedural Assignment
  • Blocking and Non-Blocking Procedural Assignment
  • Procedural Timing Control
  • Verilog Conditional Statements: if_else
  • Verilog Conditional Statements: case
  • Verilog Loop Statements
  • Introduction to Verilog Testbenches
  • System Tasks
  • Verilog Sub-Programs
  • Verilog Functions
  • Verilog Tasks
  • Verilog Compiler Directives
  • Verilog Parameters
  • Verilog Generate Statement
  • Verilog Timing Checks
  • Finite State Machines
  • Mealy Finite State Machine
  • Moore Finite State Machine
  • FSM Coding Guidelines
  • File I/O: Introduction
  • File I/O: Read Functions
  • File I/O: Write Functions
  • Targeting Xilinx FPGAs
  • User-Defined Primitives
  • Programming Language Interface

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic digital design knowledge

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Updated 9-02-2021