Embedded Systems Design
Embedded Systems Design
Core modules from this course are available as part of our embedded boot camp: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC
This course is available as private training only.
COURSE CODE: EMBD-HW
Learn general embedded concepts, tools, and techniques using the Vivado Design Suite and Vitis unified software platform.
The emphasis is on:
- Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq System on a Chip (SoC), Zynq UltraScale+™ MPSoC, Versal adaptive SoC, and MicroBlaze soft processor
- Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation
| 3-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $600/day | $1800 | 18 |
| In-Person Public Registration - $600/day | $1800 | 18 |
| Private Training | Learn More | Learn More |
| Coaching | Learn More | Learn More |
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration. | $200 | 2 |
Scheduled Classes
No Scheduled Sessions - Contact Us to ask about setting one up!
Training Duration:
3 Days
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Who should attend:
Engineers who are interested in developing embedded systems with the Zynq SoC, Zynq UltraScale+ MPSoC, Versal adaptive SoC, and/or MicroBlaze soft processor core.
Software Tools
- Vivado Design Suite
- Vitis unified software platform
Hardware
- Architectures: Zynq-7000 SoC (Cortex-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), Versal adaptive SoC (Cortex-A72 and Cortex-R5F processors), and MicroBlaze processor
- Demo board: Zynq UltraScale+ MPSoC ZCU104 or adaptive SoC VCK190 board
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the various tools that encompass an AMD Xilinx embedded design
- Rapidly architect an embedded system containing various processors using the Vivado IP integrator and Customization Wizard
- Develop software applications utilizing the Vitis unified software platform
- Create and integrate an IP-based processing system component in the Vivado Design Suite
- Design and add a custom AXI interface-based peripheral to the embedded processing system
- Simulate a custom AXI interface-based peripheral using verification IP (VIP)
- Investigate issues using cross-triggering
Course Outline
| Day 1 | Day 2 | Day 3 |
|---|---|---|
| Embedded UltraFast Design Methodology Outlines the different elements that comprise the Embedded Design Methodology. {Lecture, Demo} Overview of Embedded Hardware Development Overview of the embedded hardware development flow. {Lecture, Demo} Driving the IP Integrator Tool Describes how to access and effectively use the IPI tool. {Lecture, Lab} Overview of Embedded Software Development Reviews the process of building a user application. {Lecture} Driving the Vitis Software Development Tool Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application. {Lecture, Lab} AXI: Introduction Introduces the AXI protocol. {Lecture} | AXI: Variations Describes the differences and similarities among the three primary AXI variations. {Lecture} AXI: Transactions Describes different types of AXI transactions. {Lecture, Demo, Lab} Introduction to Interrupts Introduces the concept of interrupts, basic terminology, and generic implementation. {Lecture} Interrupts: Hardware Architecture and Support Reviews the hardware that is typically available to help implement and manage interrupts. {Lecture} AXI: Connecting AXI IP Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies. {Lecture, Demo} Creating a New AXI IP with the Wizard Explains how to use the Create and Import Wizard to create and package an AXI IP. {Lecture, Lab} AXI: BFM Simulation Using Verification IP Describes how to perform BFM simulation using the Verification IP. {Lecture, Lab} | MicroBlaze Processor Architecture Overview Overview of the MicroBlaze microprocessor architecture. {Lecture, Lab} MicroBlaze Processor Block Memory Usage Highlights how block RAM can be used with the MicroBlaze processor. {Lecture} Zynq-7000 SoC Architecture Overview Overview of the Zynq-7000 SoC architecture. {Lecture, Demo, Lab} Zynq UltraScale+ MPSoC Architecture Overview Overview of the Zynq UltraScale+ MPSoC architecture. {Lecture, Demo, Lab} Debugging Using Cross-Triggering Illustrates how hardware-software cross-triggering techniques can uncover issues. {Lecture, Lab} |
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- FPGA design experience
- Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of the Vivado software implementation tools
- Basic understanding of C programming
- Basic understanding of microprocessors
- Some HDL modeling experience