Signal Integrity and Board Design for Xilinx FPGAs

Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.

You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe signal integrity effects
  • Predict and overcome signal integrity challenges
  • Simulate signal integrity effects
  • Verify and derive design rules for the board design
  • Apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuits
  • Plan your board design under FPGA-specific restrictions
  • Supply the FPGAs with power
  • Handle thermal aspects

Learn more about signal integrity with Xilinx.

Course Outline

Day 1

  • Signal Integrity Introduction
  • Transmission Lines
  • IBIS Models and SI Tools
  • LAB: Invoking HyperLynx
    Become familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB.
  • Reflections
  • LAB: Reflection Analysis
    Define a circuit and run various simulations for effects of reflection.
  • Crosstalk
  • LAB: Crosstalk Analysis
    Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk.
  • Signal Integrity Analysis
  • Power Supply Issues
  • Signal Integrity Summary

Day 2

  • Board Design Introduction
  • FPGA Power Supply
  • LAB: Power Analysis
    Estimate initial power requirements using an Excel spreadsheet, then use the Vivado Power Analyzer to accurately predict board power needs.
  • FPGA Configuration and PCB
  • Signal Interfacing: Interfacing in General
  • Signal Interfacing: FPGA-Specific Interfacing
  • LAB: I/O Pin Planning
    Use the PlanAhead software to identify pin placement and implement pin assignments.
  • Die Architecture and Packaging
  • PCB Details
  • Thermal Aspects
  • LAB: Thermal Design
    Determine maximum junction temperature and calculate acceptable thermal resistance.
  • Tools for PCB Planning and Design
  • Board Design Summary

No Scheduled Sessions – Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
Standard Registration
30 Training Credits
Advanced Registration
Advanced Registration
27 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.


Training Duration:

3 Days

Who should attend:

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.


  • FPGA design experience preferred (Vivado Boot Camp: Basic Training course or equivalent)
  • Familiarity with high-speed PCB concepts
  • Basic knowledge of digital and analog circuit design
  • Vivado tool knowledge is helpful

Version: 2021-03-17_0932