$299/Day - Signal Integrity and Board Design for Xilinx FPGAs

Signal Integrity and Board Design for Xilinx FPGAs

Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx® FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

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(Confirmed, Closed, Full)

Training Duration:

2 Days

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Who should attend:

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe signal integrity effects
Predict and overcome signal integrity challenges
Simulate signal integrity effects
Verify and derive design rules for the board design
Apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuits
Plan your board design under FPGA-specific restrictions
Supply the FPGAs with power
Handle thermal aspects

Course Outline

Day 1	Day 2
Signal Integrity Introduction Transmission Lines IBIS Models and SI Tools LAB: Invoking HyperLynx Become familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB. Reflections LAB: Reflection Analysis Define a circuit and run various simulations for effects of reflection. Crosstalk LAB: Crosstalk Analysis Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk. Signal Integrity Analysis Power Supply Issues Signal Integrity Summary	Board Design Introduction FPGA Power Supply LAB: Power Analysis Estimate initial power requirements using an Excel spreadsheet, then use the Vivado® Power Analyzer to accurately predict board power needs. FPGA Configuration and PCB Signal Interfacing: Interfacing in General Signal Interfacing: FPGA-Specific Interfacing LAB: I/O Pin Planning Use the PlanAhead software to identify pin placement and implement pin assignments. Die Architecture and Packaging PCB Details Thermal Aspects LAB: Thermal Design Determine maximum junction temperature and calculate acceptable thermal resistance. Tools for PCB Planning and Design Board Design Summary

Day 1

Day 2

Signal Integrity Introduction
Transmission Lines
IBIS Models and SI Tools
LAB: Invoking HyperLynx
Become familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB.
Reflections
LAB: Reflection Analysis
Define a circuit and run various simulations for effects of reflection.
Crosstalk
LAB: Crosstalk Analysis
Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk.
Signal Integrity Analysis
Power Supply Issues
Signal Integrity Summary

Board Design Introduction
FPGA Power Supply
LAB: Power Analysis
Estimate initial power requirements using an Excel spreadsheet, then use the Vivado® Power Analyzer to accurately predict board power needs.
FPGA Configuration and PCB
Signal Interfacing: Interfacing in General
Signal Interfacing: FPGA-Specific Interfacing
LAB: I/O Pin Planning
Use the PlanAhead software to identify pin placement and implement pin assignments.
Die Architecture and Packaging
PCB Details
Thermal Aspects
LAB: Thermal Design
Determine maximum junction temperature and calculate acceptable thermal resistance.
Tools for PCB Planning and Design
Board Design Summary

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

FPGA design experience preferred (Vivado Boot Camp: Basic Training course or equivalent)
Familiarity with high-speed PCB concepts
Basic knowledge of digital and analog circuit design
Vivado tool knowledge is helpful

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Updated 11-13-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.