Signal Integrity and Board Design for Xilinx FPGAs
Signal Integrity and Board Design for Xilinx FPGAs
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx® FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
2-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $299/day | $598 | 6 |
In-Person Registration - $399/day | $798 | 8 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
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