Designing FPGAs Using the Vivado Design Suite 2

This course shows you how to build an effective FPGA design using synchronous design techniques, using the Vivado IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Create a Tcl script to create a project, add sources, and implement a design
  • Describe and use the clock resources in a design
  • Build resets into your system for optimum reliability and design speed
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Describe the HLx design flow that increases productivity
  • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline

Day 1

  • UltraFast® Design Methodology: Design Creation and Analysis
    Overview of the methodology guidelines covered in this course.
  • Synchronous Design Techniques
    Introduces synchronous design techniques used in an FPGA design.
  • Resets
    Investigates the impact of using asynchronous resets in a design.
  • Register Duplication
    Use register duplication to reduce high fanout nets in a design.
  • Scripting in Vivado Design Suite Project Mode
    Explains how to write Tcl commands in the project-based flow for a design.
  • Clocking Resources
    Describes various clock resources, clocking layout, and routing in a design.
  • I/O Logic Resources
    Overview of I/O resources and the IOB property for timing closure.
  • Creating and Packaging Custom IP
    Create your own IP and package and include it in the Vivado IP catalog.
  • Using an IP Container
    Use a core container file as a single file representation for an IP.
  • Designing with IP Integrator
    Use the Vivado IP integrator to create the uart_led subsystem.

Day 2

  • Timing Summary Report
    Use the post-implementation timing summary report to sign-off criteria for timing closure.
  • Generated Clocks
    Use the report clock networks report to determine if there are any generated clocks in a design.
  • Clock Group Constraints
    Apply clock group constraints for asynchronous clock domains.
  • Introduction to Timing Exceptions
    Introduces timing exception constraints and applying them to fine tune design timing.
  • Power Analysis and Optimization Using the Vivado Design Suite
    Use report power commands to estimate power consumption.
  • Introduction to the HLx Design Flow
    Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
  • Configuration Process
    Understand the FPGA configuration process, such as device power up, CRC check, etc.
  • Sampling and Capturing Data in Multiple Clock Domains
    Overview of debugging a design with multiple clock domains that require multiple ILAs.
  • Design Analysis Using Tcl Commands
    Analyze a design using Tcl commands.

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

Version: 2019-08-08_1417