Designing FPGAs Using the Vivado Design Suite 2

Designing FPGAs Using the Vivado Design Suite 2 – Clocking, IO, IP Integrator

COURSE CODE: FPGA-VDES2

Learn how to build a more effective FPGA design.

The focus is on:

Using synchronous design techniques
Utilizing the Vivado IP integrator to create a sub-system
Performing power analysis and optimization to improve the power efficiency of a design
Reviewing and analyzing timing reports for a design

This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$200	2

Scheduled Classes

Live Online Training (Starts at 9am ET)

November 4-6, 2025 | Register Today

Training Duration:

3 Days

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

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Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to AMD FPGAs.

Software Tools

Vivado Design Suite

Hardware

Architecture: UltraScale FPGAs
Demo board (optional): Zynq UltraScale+ MPSoC ZCU104 board*

* This course focuses on the UltraScale architecture

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Identify synchronous design techniques
Build resets into your system for optimum reliability and design speed
Create a Tcl script to create a project, add sources, and implement a design
Describe and use the clock resources in a design
Create and package your own IP and add to the Vivado IP catalog for reuse
Use the Vivado IP integrator to create a block design
Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
Perform power analysis and optimization
Describe the HDL instantiation flow of the Vivado logic analyzer

Course Outline

Day 1	Day 2	Day 3
UltraFast Design Methodology UltraFast Design Methodology: Design Creation Introduces the UltraFast methodology guidelines on design creation. {Lecture} Design Techniques Synchronous Design Techniques Introduces the synchronous design techniques used in an FPGA design. {Lecture} Resets Investigates the impact of using asynchronous resets in a design. {Lecture, Lab} Register Duplication Covers the use of register duplication to reduce high fanout nets in a design. {Lecture} Using Tcl Commands in the Vivado Design Suite Project Flow Introduces basic Tcl commands and executing a Tcl script. {Lecture, Lab} Scripting in Vivado Design Suite Non-Project Mode Demonstrates how to write Tcl commands in the non-project batch flow for a design. {Lecture, Lab} Clocking in the UltraScale Architecture Clock Structure and Layout in the UltraScale Architecture Describes UltraScale clocking architecture and differences in the clocking architectures between 7 series and UltraScale FPGAs. {Lecture, Lab} Clock Buffers in the UltraScale Architecture Reviews the different clock buffers and clock migration. {Lecture} Clock Management in the UltraScale Architecture Highlights clock management resources. {Lecture} Clock Routing in the UltraScale Architecture Describes clock routing, distribution, and the benefits of clock routing. {Lecture}	I/O in the UltraScale Architecture UltraScale Architecture I/O Resources: Overview Provides an overview of the I/O resources and I/O banks available the UltraScale architecture. {Lecture} UltraScale Architecture I/O Resources: Component Mode Describes component mode, SelectIO™ interface logic, SERDES technology, and programmable delay lines. {Lecture} UltraScale Architecture I/O Resources: Native Mode Describes SelectIO interface logic, BITSLICE technology, native mode clocking, and the High Speed SelectIO Wizard. {Lecture} IP Integrator Getting Started with Vivado IP Integrator Introduces the Vivado IP integrator tool and its features. Also reviews creating and working with block designs. {Lecture, Demo, Lab} Designing IP Subsystems Using Vivado IP Integrator Illustrates designing with processor-based subsystems and working with custom RTL code. Also explains how to create Vitis™ platforms using Vivado IP integrator. {Lecture} Block Design Containers in the Vivado IP Integrator Describes the block design container (BDC) feature and shows how to create a BDC in the IP integrator. {Lecture} Creating and Packaging Custom IP Covers creating your own IP and package and including it in the Vivado IP catalog. {Lecture, Lab} Using an IP Container Illustrates how to use a core container file as a single file representation for an IP. {Lecture, Demo}	Timing – Intermediate Report Clock Networks Demonstrates how to use the report_clock_networks command to view the primary and generated clocks in a design. {Lecture, Demo} Timing Summary Report Reviews how to use the post-implementation timing summary report to sign off for timing closure. {Lecture, Demo} Clock Group Constraints Describes applying clock group constraints for asynchronous clock domains. {Lecture, Demo} Introduction to Timing Exceptions Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo, Lab} Power Power Analysis and Optimization Using the Vivado Design Suite Illustrates using report power commands to estimate power consumption. {Lecture, Lab} Configuration Configuration Process Reviews the FPGA configuration process, such as device power up and CRC checks. {Lecture} Debugging HDL Instantiation Debug Probing Flow Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer. {Lecture, Lab}

Day 1

Day 2

Day 3

UltraFast Design Methodology

UltraFast Design Methodology: Design Creation Introduces the UltraFast methodology guidelines on design creation. {Lecture}

Design Techniques

Synchronous Design Techniques Introduces the synchronous design techniques used in an FPGA design. {Lecture}
Resets Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
Register Duplication Covers the use of register duplication to reduce high fanout nets in a design. {Lecture}
Using Tcl Commands in the Vivado Design Suite Project Flow Introduces basic Tcl commands and executing a Tcl script. {Lecture, Lab}
Scripting in Vivado Design Suite Non-Project Mode Demonstrates how to write Tcl commands in the non-project batch flow for a design. {Lecture, Lab}

Clocking in the UltraScale Architecture

Clock Structure and Layout in the UltraScale Architecture Describes UltraScale clocking architecture and differences in the clocking architectures between 7 series and UltraScale FPGAs. {Lecture, Lab}
Clock Buffers in the UltraScale Architecture Reviews the different clock buffers and clock migration. {Lecture}
Clock Management in the UltraScale Architecture Highlights clock management resources. {Lecture}
Clock Routing in the UltraScale Architecture Describes clock routing, distribution, and the benefits of clock routing. {Lecture}

I/O in the UltraScale Architecture

UltraScale Architecture I/O Resources: Overview
Provides an overview of the I/O resources and I/O banks available the UltraScale architecture. {Lecture}
UltraScale Architecture I/O Resources: Component Mode
Describes component mode, SelectIO™ interface logic, SERDES technology, and programmable delay lines. {Lecture}
UltraScale Architecture I/O Resources: Native Mode
Describes SelectIO interface logic, BITSLICE technology, native mode clocking, and the High Speed SelectIO Wizard. {Lecture}

IP Integrator

Getting Started with Vivado IP Integrator
Introduces the Vivado IP integrator tool and its features. Also reviews creating and working with block designs. {Lecture, Demo, Lab}
Designing IP Subsystems Using Vivado IP Integrator
Illustrates designing with processor-based subsystems and working with custom RTL code. Also explains how to create Vitis™ platforms using Vivado IP integrator. {Lecture}
Block Design Containers in the Vivado IP Integrator
Describes the block design container (BDC) feature and shows how to create a BDC in the IP integrator. {Lecture}
Creating and Packaging Custom IP
Covers creating your own IP and package and including it in the Vivado IP catalog. {Lecture, Lab}
Using an IP Container
Illustrates how to use a core container file as a single file representation for an IP. {Lecture, Demo}

Timing – Intermediate

Report Clock Networks
Demonstrates how to use the report_clock_networks command to view the primary and generated clocks in a design. {Lecture, Demo}
Timing Summary Report
Reviews how to use the post-implementation timing summary report to sign off for timing closure. {Lecture, Demo}
Clock Group Constraints
Describes applying clock group constraints for asynchronous clock domains. {Lecture, Demo}
Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo, Lab}

Power

Power Analysis and Optimization Using the Vivado Design Suite
Illustrates using report power commands to estimate power consumption. {Lecture, Lab}

Configuration

Configuration Process
Reviews the FPGA configuration process, such as device power up and CRC checks. {Lecture}

Debugging

HDL Instantiation Debug Probing Flow
Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Intermediate HDL knowledge (Verilog or VHDL)
Digital design knowledge and experience (attendees should be electrical engineers)
Experience with the basics of the Tcl language
Designing FPGAs Using the Vivado Design Suite 1 course (recommended)

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Updated 03-12-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

Designing FPGAs Using the Vivado Design Suite 2 – Clocking, IO, IP Integrator