Designing FPGAs Using the Vivado™ Design Suite 2
Designing FPGAs Using the Vivado™ Design Suite 2
This course shows you how to build an effective FPGA design using synchronous design techniques, using the Vivado™ IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.
Skills Gained
After completing this comprehensive training, you will know how to:
- Create a Tcl script to create a project, add sources, and implement a design
- Describe and use the clock resources in a design
- Build resets into your system for optimum reliability and design speed
- Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
- Use the Vivado™ IP integrator to create a block design
- Create and package your own IP and add to the Vivado™ IP catalog to reuse
- Describe the HLx design flow that increases productivity
- Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado™ logic analyzer
- Identify synchronous design techniques
- Describe how an FPGA is configured
Course Outline
Day 1
- UltraFast® Design Methodology: Design Creation and AnalysisOverview of the methodology guidelines covered in this course.
- Synchronous Design TechniquesIntroduces synchronous design techniques used in an FPGA design.
- ResetsInvestigates the impact of using asynchronous resets in a design.
- Register DuplicationUse register duplication to reduce high fanout nets in a design.
- Scripting in Vivado™ Design Suite Project ModeExplains how to write Tcl commands in the project-based flow for a design.
- Clocking ResourcesDescribes various clock resources, clocking layout, and routing in a design.
- I/O Logic ResourcesOverview of I/O resources and the IOB property for timing closure.
- Creating and Packaging Custom IPCreate your own IP and package and include it in the Vivado™ IP catalog.
- Using an IP ContainerUse a core container file as a single file representation for an IP.
- Designing with IP IntegratorUse the Vivado™ IP integrator to create the uart_le
Day 2
- Timing Summary ReportUse the post-implementation timing summary report to sign-off criteria for timing closure.
- Generated ClocksUse the report clock networks report to determine if there are any generated clocks in a design.
- Clock Group ConstraintsApply clock group constraints for asynchronous clock domains.
- Introduction to Timing ExceptionsIntroduces timing exception constraints and applying them to fine tune design timing.
- Power Analysis and Optimization Using the Vivado™ Design SuiteUse report power commands to estimate power consumption.
- Introduction to the HLx Design FlowUse the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
- Configuration ProcessUnderstand the FPGA configuration process, such as device power up, CRC check, etc.
- Sampling and Capturing Data in Multiple Clock DomainsOverview of debugging a design with multiple clock domains that require multiple ILAs.
- Design Analysis
No Scheduled Sessions - Contact Us to ask about setting one up!
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Training Duration:
2 Days
Who should attend:
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Prerequisites
Designing FPGAs Using the Vivado™ Design Suite 1 course
Working HDL knowledge (VHDL or Verilog)
Digital design experience
Software Tools
Vivado™ System Edition 2017.1
Hardware
Architecture: Ultrascale™ and 7 series FPGAs*Demo board (optional): Kintex-7 FPGA KC705 board** This course focuses on the Ultrascale™ and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.