Designing FPGAs Using the Vivado Design Suite 4

This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
  • Analyze a timing report to identify how to center the clock in the data eye
  • Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports
  • Utilize floorplanning techniques to improve design performance
  • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
  • Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
  • Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
  • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1

  • UltraFast® Design Methodology: Advanced TechniquesIntroduces the UltraFast® methodology guidelines covered in this course.
  • Scripting in Vivado Design Suite Non-Project ModeWrite Tcl commands in the non-project batch flow for a design.
  • Hierarchical DesignOverview of the hierarchical design flows in the Vivado Design Suite.
  • Managing Remote IPStore IP and related files remote to the current working project directory.
  • I/O Timing ScenariosOverview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
  • Source-Synchronous I/O TimingApply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
  • System-Synchronous I/O TimingApply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
  • Timing Constraints PriorityIdentify the priority of timing constraints.
  • Case AnalysisUnders

Day 2

  • Physical OptimizationUse physical optimization techniques for timing closure.
  • Vivado Design Suite ECO FlowUse ECO flow to make changes to a previously implemented design and apply changes to the original design.
  • Power Management TechniquesIdentify techniques used for low power design.
  • Daisy Chains and Gangs in ConfigurationIntroduces advanced configuration schemes for multiple FPGAs.
  • Bitstream SecurityUnderstand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.
  • Vivado Design Suite Debug MethodologyEmploy the debug methodology for debugging a design using the Vivado logic analyzer.
  • Trigger and Debug at Device StartupDebug the events around the device startup.
  • Debugging the Design Using Tcl CommandsUse Tcl scripting for VLA designs for adding probes and making connections to probes.
  • Using Procedures in Tcl ScriptingEmploy procedures in Tcl scripting.
  • Using Lists in Tcl Scriptin

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,600
Standard Registration
16 Training Credits
Advanced Registration
$1,400
Advanced Registration
14 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$700
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

Prerequisites

Designing FPGAs Using the Vivado Design Suite 2 courseDesigning FPGAs Using the Vivado Design Suite 3> course

At least six months of design experience with Xilinx tools and FPGAs

Software Tools

Vivado System Edition 2017.1

Hardware

Architecture: Ultrascale and 7 series FPGAs*Demo board: Kintex-7 FPGA KC705 board** This course focuses on the Ultrascale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626