$299/Day - Designing FPGAs Using the Vivado Design Suite 4

Designing FPGAs Using the Vivado Design Suite 4

BLT offers this Xilinx^® course under the name Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure.

This course on FPGAs tackles the most sophisticated aspects of the Vivado^® Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (mailed to you)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

See available class dates for Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure

Training Duration:

2 Days

We update our schedule regularly. Stay informed.

NEWSLETTER SIGNUP

Who should attend:

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity.

Skills Gained

After completing this comprehensive training, you will know how to:

Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
Analyze a timing report to identify how to center the clock in the data eye
Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports
Utilize floorplanning techniques to improve design performance
Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1	Day 2
UltraFast^™ Design Methodology: Advanced Techniques Introduces the UltraFast methodology guidelines covered in this course. Scripting in Vivado Design Suite Non-Project Mode Write Tcl commands in the non-project batch flow for a design. Hierarchical Design Overview of the hierarchical design flows in the Vivado Design Suite. Managing Remote IP Store IP and related files remote to the current working project directory. I/O Timing Scenarios Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data. Source-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface. System-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface. Timing Constraints Priority Identify the priority of timing constraints. Case Analysis Understand how to analyze timing when using multiplexed clocks in a design. Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks while floorplanning. Design Analysis and Floorplanning Explore the pre- and post-implementation design analysis features of the Vivado IDE. Incremental Compile Flow Utilize the incremental compile flow when making last-minute RTL changes.	Physical Optimization Use physical optimization techniques for timing closure. Vivado Design Suite ECO Flow Use ECO flow to make changes to a previously implemented design and apply changes to the original design. Power Management Techniques Identify techniques used for low power design. Daisy Chains and Gangs in Configuration Introduces advanced configuration schemes for multiple FPGAs. Bitstream Security Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication. Vivado Design Suite Debug Methodology Employ the debug methodology for debugging a design using the Vivado logic analyzer. Trigger and Debug at Device Startup Debug the events around the device startup. Debugging the Design Using Tcl Commands Use Tcl scripting for VLA designs for adding probes and making connections to probes. Using Procedures in Tcl Scripting Employ procedures in Tcl scripting. Using Lists in Tcl Scripting Employ lists in Tcl Scripting Using regexp in Tcl Scripting Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite. Debugging and Error Management in Tcl Scripting Understand how to debug errors in a Tcl Script.

Day 1

Day 2

UltraFast^™ Design Methodology: Advanced Techniques
Introduces the UltraFast methodology guidelines covered in this course.
Scripting in Vivado Design Suite Non-Project Mode
Write Tcl commands in the non-project batch flow for a design.
Hierarchical Design
Overview of the hierarchical design flows in the Vivado Design Suite.
Managing Remote IP
Store IP and related files remote to the current working project directory.
I/O Timing Scenarios
Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
Source-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
System-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
Timing Constraints Priority
Identify the priority of timing constraints.
Case Analysis
Understand how to analyze timing when using multiplexed clocks in a design.
Introduction to Floorplanning
Introduction to floorplanning and how to use Pblocks while floorplanning.
Design Analysis and Floorplanning
Explore the pre- and post-implementation design analysis features of the Vivado IDE.
Incremental Compile Flow
Utilize the incremental compile flow when making last-minute RTL changes.

Physical Optimization
Use physical optimization techniques for timing closure.
Vivado Design Suite ECO Flow
Use ECO flow to make changes to a previously implemented design and apply changes to the original design.
Power Management Techniques
Identify techniques used for low power design.
Daisy Chains and Gangs in Configuration
Introduces advanced configuration schemes for multiple FPGAs.
Bitstream Security
Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.
Vivado Design Suite Debug Methodology
Employ the debug methodology for debugging a design using the Vivado logic analyzer.
Trigger and Debug at Device Startup
Debug the events around the device startup.
Debugging the Design Using Tcl Commands
Use Tcl scripting for VLA designs for adding probes and making connections to probes.
Using Procedures in Tcl Scripting
Employ procedures in Tcl scripting.
Using Lists in Tcl Scripting
Employ lists in Tcl Scripting
Using regexp in Tcl Scripting
Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite.
Debugging and Error Management in Tcl Scripting
Understand how to debug errors in a Tcl Script.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Designing FPGAs Using the Vivado Design Suite 2
Designing FPGAs Using the Vivado Design Suite 3
At least six months of design experience with Xilinx tools and FPGAs

RELATED COURSES:

Updated 4-10-22

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