Designing FPGAs Using the Vivado Design Suite 4

Designing FPGAs Using the Vivado Design Suite 4 – Timing Closure, Floorplanning, Debugging and Tcl

COURSE CODE: FPGA-VDES4

Learn how to use the advanced aspects of the Vivado Design Suite.

The focus is on:

Applying techniques to reduce delay and to improve clock skew and clock uncertainty
Utilizing floorplanning techniques
Employing advanced implementation options
Utilizing AMD security features
Identifying advanced FPGA configurations
Debugging a design at the device startup phase
Utilizing Tcl scripting when using the Vivado logic analyzer in a design

This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

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Who should attend:

Engineers who seek advanced training in using AMD tools to improve FPGA performance and utilization while also increasing productivity.

Software Tools

Vivado Design Suite

Hardware

Architecture: UltraScale FPGAs*
Demo board: Zynq UltraScale+ ZCU104 board*

* This course focuses on the UltraScale architectures. C

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Analyze a timing report to identify how to center the clock in the data eye
Apply appropriate techniques to reduce logic and net delay and to improve clock skew and clock uncertainty
Implement Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
Utilize floorplanning techniques to improve design performance
Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
Utilize security features, bitstream encryption, and authentication using AES for design and IP security
Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset
Utilize Tcl scripting when using the Vivado logic analyzer in a design

Course Outline

Day 1	Day 2	Day 3
UltraFast Design Methodology (UFDM) UltraFast Design Methodology: Timing Closure Introduces the UltraFast methodology guidelines on timing closure. {Lecture} Vivado Tool Flow Hierarchical Design Provides an overview of the hierarchical design flows in the Vivado Design Suite. {Lecture} Incremental Compile Flow Demonstrates how to utilize the incremental compile flow when making last-minute RTL changes. {Lecture, Lab} Vivado Design Suite ECO Flow Illustrates using the ECO flow for making changes to a previously implemented design and applying the changes to the original design. {Lecture, Lab} Vivado IP Catalog Managing IP in Remote Locations Covers storing IP and related files that are remote to the current working project directory. {Lecture, Lab} Timing – Advanced Timing Closure Using Physical Optimization Techniques Describes physical optimization techniques for timing closure. {Lecture, Lab} Reducing Logic Delay Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture} Reducing Net Delay Reviews different techniques to reduce congestion and net delay. {Lecture}	Improving Clock Skew Describes how to apply various techniques to improve clock skew. {Lecture} Improving Clock Uncertainty Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab} Design Runs Intelligent Design Runs (IDR) Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab} Power Power Management Techniques Describes the techniques used for low power design. {Lecture} Floorplanning Introduction to Floorplanning Provides an introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture} Design Analysis and Floorplanning Highlights the pre- and post-implementation design analysis features of the Vivado IDE. {Lecture, Lab} Congestion Identifies congestion and addresses congestion issues. {Lecture} Configuration Daisy Chains and Gangs in Configuration Introduces advanced configuration schemes for multiple FPGAs. {Lecture} Bitstream Security Reviews AMD bitstream security features, such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}	Debugging Vivado Design Suite Debug Methodology Covers debug core recommendations and how to employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture} Trigger and Debug at Device Startup Shows how to debug the events around device startup. {Lecture, Demo} Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Illustrates using trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer. {Lecture, Lab} Vivado Store Introduction to the Vivado Store Introduces the Vivado Store. {Lecture, Demo} Tcl Commands Debugging a Design Using Tcl Commands Reviews how to use Tcl scripting for VLA designs when adding probes and making connections to probes. {Lecture, Lab} Using Procedures in Tcl Scripting Discusses employing procedures in Tcl scripting. {Lecture} Using Lists in Tcl Scripting Covers how to employ lists in Tcl scripting. {Lecture} Using Regular Expressions in Tcl Scripting Highlights how to use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite. {Lecture, Lab} Debugging and Error Handling in Tcl Scripts Describes how to debug errors using Tcl scripts. {Lecture}

Day 1

Day 2

Day 3

UltraFast Design Methodology (UFDM)

UltraFast Design Methodology: Timing Closure
Introduces the UltraFast methodology guidelines on timing closure. {Lecture}

Vivado Tool Flow

Hierarchical Design
Provides an overview of the hierarchical design flows in the Vivado Design Suite. {Lecture}
Incremental Compile Flow
Demonstrates how to utilize the incremental compile flow when making last-minute RTL changes. {Lecture, Lab}
Vivado Design Suite ECO Flow
Illustrates using the ECO flow for making changes to a previously implemented design and applying the changes to the original design. {Lecture, Lab}

Vivado IP Catalog

Managing IP in Remote Locations
Covers storing IP and related files that are remote to the current working project directory. {Lecture, Lab}

Timing – Advanced

Timing Closure Using Physical Optimization Techniques
Describes physical optimization techniques for timing closure. {Lecture, Lab}
Reducing Logic Delay
Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}
Reducing Net Delay
Reviews different techniques to reduce congestion and net delay. {Lecture}

Improving Clock Skew
Describes how to apply various techniques to improve clock skew. {Lecture}
Improving Clock Uncertainty
Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}

Design Runs

Intelligent Design Runs (IDR) Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}

Power

Power Management Techniques Describes the techniques used for low power design. {Lecture}

Floorplanning

Introduction to Floorplanning Provides an introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
Design Analysis and Floorplanning Highlights the pre- and post-implementation design analysis features of the Vivado IDE. {Lecture, Lab}
Congestion Identifies congestion and addresses congestion issues. {Lecture}

Configuration

Daisy Chains and Gangs in Configuration Introduces advanced configuration schemes for multiple FPGAs. {Lecture}
Bitstream Security Reviews AMD bitstream security features, such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}

Debugging

Vivado Design Suite Debug Methodology
Covers debug core recommendations and how to employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}
Trigger and Debug at Device Startup
Shows how to debug the events around device startup. {Lecture, Demo}
Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
Illustrates using trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer. {Lecture, Lab}

Vivado Store

Introduction to the Vivado Store
Introduces the Vivado Store. {Lecture, Demo}

Tcl Commands

Debugging a Design Using Tcl Commands
Reviews how to use Tcl scripting for VLA designs when adding probes and making connections to probes. {Lecture, Lab}
Using Procedures in Tcl Scripting
Discusses employing procedures in Tcl scripting. {Lecture}
Using Lists in Tcl Scripting
Covers how to employ lists in Tcl scripting. {Lecture}
Using Regular Expressions in Tcl Scripting
Highlights how to use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite. {Lecture, Lab}
Debugging and Error Handling in Tcl Scripts
Describes how to debug errors using Tcl scripts. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Intermediate HDL knowledge (Verilog or VHDL)
Sound digital design background
Designing FPGAs Using the Vivado Design Suite 1 (recommended)
Designing FPGAs Using the Vivado Design Suite 2 (recommended)
Designing FPGAs Using the Vivado Design Suite 3 (recommended)

RELATED COURSES:

Updated 03-12-2025

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Designing FPGAs Using the Vivado Design Suite 4 – Timing Closure, Floorplanning, Debugging and Tcl