Designing with the Versal Adaptive SoC: Design Methodology

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Designing with the Versal Adaptive SoC: Design Methodology

Course Code: ACAP-VDM

BLT helped create the UltraFast Design Methodology for Xilinx (now AMD) which this course is based on. Learn more about the history of the methodology here.

Use different AMD Versal adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application partitioning, design closure, power, and thermal solutions to enhance the performance of a design.

The emphasis of this course is on:

  • Demonstrating the embedded software development flow for Versal devices
  • Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
  • Leveraging the Power Design Manager (PDM) tool for power estimation
  • Identifying Versal adaptive SoC power and thermal solutions
  • Applying common timing closure techniques
  • Performing system-level simulation and debugging
  • Improving Versal adaptive SoC system performance

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

REGISTER

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

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Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about the Versal design methodology.

Software Tools

  • Vivado Design Suite
  • Vitis Unified IDE
  • PetaLinux Tools

Hardware

  • Architecture: Versal adaptive SoC
  • Demo board: Versal VCK190 Evaluation Platform

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the embedded software development flow for AMD Versal devices
  • Use the provided design tools and Versal adaptive SoC design methodologies to create complex systems
  • Leverage the Power Design Manager (PDM) tool for power estimation for Versal devices
  • Identify Versal adaptive SoC power and thermal solutions
  • Create a custom AMD Vitis platform to run acceleration applications
  • Identify and apply common timing closure techniques
  • Describe the different debugging options available for the Versal adaptive SoC
  • Perform system-level simulation and debugging

Course Outline

Day 1Day 2Day 3
  • Board System Design Methodology
    Describes PCB, power, clocking, and I/O considerations when designing a system. {Lecture}
  • Embedded Software Development
    Describes the software development environments and embedded software development flows for Versal devices. Also introduces embedded software debugging. {Lecture, Lab}
  • Software Build Flow
    Provides an overview of the different build flows, such as the doit-yourself, Yocto Project, and PetaLinux tool flows. {Lecture, Lab}
  • Software Stack
    Reviews the Versal device bare-metal, FreeRTOS, and Linux software stack and their components. {Lecture}
  • Security Management and Safety Features Describes the security management and safety features of the Versal devices. {Lecture}
  • System and Solution Planning Methodology
    Describes design partitioning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning. {Lecture}
  • Application Partitioning 1
    Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed. {Lecture}
  • Power Design Manager
    Discusses using the new Power Design Manager tool, including import and export functions. {Lecture, Lab}
  • Power and Thermal Solutions
    Discusses the power domains in the Versal adaptive SoC as well as power optimization and analysis techniques. Thermal design challenges are also covered. {Lecture}
  • Hardware, IP, and Platform Development Methodology
    Describes the different Versal device design flows and covers the custom platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis environment. {Lecture, Lab}
  • Timing Closure Overview
    Describes the timing closure and baselining of a design. Also explains QoR reports and timing violation analysis. {Lecture}
  • Timing Closure Techniques
    Lists the common timing closure techniques for logic optimization, design analysis, and timing closure. Also describes the timing considerations for SSI technology devices. {Lecture}
  • System Integration and Validation Methodology
    Describes different simulation flows as well as timing and power closure techniques. Also explains how to improve system performance. {Lecture}
  • Configuration and Debugging
    Describes the configuration and debug process for the Versal devices. Also covers the Versal device debug interfaces, such as the test access port (TAP) and debug access port (DAP) controller. {Lecture}
  • Overview of HSDP
    Describes the high-speed debug port (HSDP) in the Versal device. Also goes over the steps to use the SmartLynq+ module for high-speed debugging. {Lecture, Lab}
  • Fabric Debug
    Explains the fabric debug features available in the Versal devices and reviews the different debug IP cores supported for the Versal devices, such as the AXI Debug Hub, AXIS ILA, and AXIS VIO. {Lecture, Lab}
  • System Simulation
    Explains how to perform system-level simulation in a Versal device design. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic knowledge of AMD FPGAs and adaptive SoCs
  • Basic knowledge of the Vivado and Vitis tools

RELATED COURSES:

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Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

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