C-based Design: High-Level Synthesis with the Vivado HLx Tool

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

NEWER COURSE: A newer version of this content is available in this class: High-Level Synthesis with the Vitis HLS Tool

COURSE CODE: DSP HLS

The course provides a thorough introduction to the Vivado High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1200	12
In-Person Public Registration - $600/day	$1200	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

See available class dates for High-Level Synthesis with the Vitis HLS Tool.

Training Duration:

2 Days

REQUEST COURSE

Be the first to know. Sign up for our newsletter.

Who should attend:

Software and hardware engineers looking to utilize high-level synthesis.

Skills Gained

After completing this comprehensive training, you will know how to:

Enhance productivity by using the Vivado HLS tool
Describe the high-level synthesis flow
Use the Vivado tool HLS for a first project
Identify the importance of the testbench
Use directives to improve performance and area and select RTL interfaces
Identify common coding pitfalls as well as methods for improving code for RTL/hardware
Perform system-level integration of IP generated by the Vivado HLS tool
Describe how to use OpenCV functions in the Vivado HLS tool

Course Outline

Day 1	Day 2
Introduction to High-Level Synthesis Overview of the High-level Synthesis (HLS), Vivado HLS tool flow, and the verification advantage. Basics of the Vivado HLS Tool Explore the basics of high-level synthesis and the Vivado HLS tool. Design Exploration with Directives Explore different optimization techniques that can improve the design performance. Vivado HLS Tool Command Line Interface Describes the Vivado HLS tool flow in command prompt mode. Introduction to HLS UltraFast^® Design Methodology Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps. Introduction to I/O Interfaces Explains interfaces such as block-level and port-level protocols abstracted by the Vivado HLS tool from the C design. Block-Level Protocols Explains the different types of block-level protocols abstracted by the Vivado HLS tool. Port-Level Protocols Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design. Port-Level Protocols: AXI4 Interfaces Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave) and AXI4-Stream) supported by the Vivado HLS tool. Port-Level Protocols: Memory Interfaces Describes the Memory Interface port-level protocols (such as BRAM, FIFO) abstracted by the Vivado HLS tool from the C design. Port-Level Protocols: Bus Protocol Explains the bus protocol supported by the Vivado HLS tool. Pipeline for Performance: PIPELINE Describes the PIPELINE directive for improving the throughput of a design.	Pipeline for Performance: DATAFLOW Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to executes as soon as possible. Optimizing Structures for Performance Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance. Data Pack and Data Dependencies Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design. Vivado HLS Tool Default Behavior: Latency Describes the default behavior of the Vivado HLS tool on latency and throughput. Reduce Latency Describes how to optimize the C design to improve latency. Improving Area Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. Introduction to HLx Design Flow Describes the traditional RTL flow versus the Vivado HLx design flow. HLS vs. SDSoC^® Development Environment Flow Describes the HLS flow versus the SDSoC development environment flow. Vivado HLS Tool: C Code Describes the Vivado^™ HLS tool support for the C/C++ languages, as well as arbitrary precision data types. Hardware Modeling Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class. OpenCV Libraries Explains the OpenCV design flow and the Vivado HLS tool support. Pointers Explains the use of pointers in the design and workarounds for some of the limitations.

Day 1

Day 2

Introduction to High-Level Synthesis
Overview of the High-level Synthesis (HLS), Vivado HLS tool flow, and the verification advantage.
Basics of the Vivado HLS Tool
Explore the basics of high-level synthesis and the Vivado HLS tool.
Design Exploration with Directives
Explore different optimization techniques that can improve the design performance.
Vivado HLS Tool Command Line Interface
Describes the Vivado HLS tool flow in command prompt mode.
Introduction to HLS UltraFast^® Design Methodology
Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps.
Introduction to I/O Interfaces
Explains interfaces such as block-level and port-level protocols abstracted by the Vivado HLS tool from the C design.
Block-Level Protocols
Explains the different types of block-level protocols abstracted by the Vivado HLS tool.
Port-Level Protocols
Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design.
Port-Level Protocols: AXI4 Interfaces
Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave) and AXI4-Stream) supported by the Vivado HLS tool.
Port-Level Protocols: Memory Interfaces
Describes the Memory Interface port-level protocols (such as BRAM, FIFO) abstracted by the Vivado HLS tool from the C design.
Port-Level Protocols: Bus Protocol
Explains the bus protocol supported by the Vivado HLS tool.
Pipeline for Performance: PIPELINE
Describes the PIPELINE directive for improving the throughput of a design.

Pipeline for Performance: DATAFLOW
Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to executes as soon as possible.
Optimizing Structures for Performance
Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance.
Data Pack and Data Dependencies
Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design.
Vivado HLS Tool Default Behavior: Latency
Describes the default behavior of the Vivado HLS tool on latency and throughput.
Reduce Latency
Describes how to optimize the C design to improve latency.
Improving Area
Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.
Introduction to HLx Design Flow
Describes the traditional RTL flow versus the Vivado HLx design flow.
HLS vs. SDSoC^® Development Environment Flow
Describes the HLS flow versus the SDSoC development environment flow.
Vivado HLS Tool: C Code
Describes the Vivado^™ HLS tool support for the C/C++ languages, as well as arbitrary precision data types.
Hardware Modeling
Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class.
OpenCV Libraries
Explains the OpenCV design flow and the Vivado HLS tool support.
Pointers
Explains the use of pointers in the design and workarounds for some of the limitations.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

C, C++, or System C knowledge
High-level synthesis for software engineers OR high-level synthesis for hardware engineers

RELATED COURSES:

Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

REQUEST COURSE

Updated 12-18-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.