PCIe Protocol Overview

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

NEWER COURSE: A newer version of this content is available in this class: Designing an Integrated PCI Express System.

Please contact the BLT Training Team to schedule a private class.

This PCIe Protocol Overview course focuses on the fundamentals of the PCI Express protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.

Implementation issues are covered in the two-day Designing an Integrated PCI Express System course.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Interpret various transactions occurring on the link
  • Describe the layered architecture and the tasks and packet types each is responsible for
  • Properly estimate maximum performance of a link
  • Illustrate how errors can be communicated within the system
  • Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits

More about the PCI Express and Xilinx® Technology.

Course Outline

Day 1

  • Introduction
  • Introduction to the PCIe Architecture
  • Review of the PCIe Protocol
  • Packet Formatting Details
  • LAB: Packet Decoding
    This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.
  • Packet Routing
  • Interrupts and Error Management
  • Summary

Training Duration:

1 Day

Who should attend:

FPGA designers, logic designers, and anyone who needs an in-depth knowledge of the PCI Express protocol



Version: 2021-12-08
Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.