PCIe Protocol Overview

This course focuses on the fundamentals of the PCI Express protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed. Implementation issues are covered in the two-day Designing an Integrated PCI Express System course.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Interpret various transactions occurring on the link
  • Describe the layered architecture and the tasks and packet types each is responsible for
  • Properly estimate maximum performance of a link
  • Illustrate how errors can be communicated within the system
  • Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits

Course Outline

Day 1

  • Introduction
  • Introduction to the PCIe Architecture
  • Review of the PCIe Protocol
  • Packet Formatting Details
  • Lab 1: Packet DecodingThis lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.
  • Packet Routing
  • Interrupts and Error Management
  • Summary

Scheduled Classes

Columbia, MD
6/28/2019 - 6/28/2019
Columbia, MD
8/8/2019 - 8/8/2019
Sterling, Virginia
8/15/2019 - 8/15/2019
Parsippany, NJ
9/12/2019 - 9/12/2019
Trevose, PA
9/12/2019 - 9/12/2019
Hauppauge, NY
9/19/2019 - 9/19/2019
Rochester, NY
10/3/2019 - 10/3/2019
Sterling, Virginia
11/21/2019 - 11/21/2019

Education Investment Options

Standard Registration
$900
Standard Registration
9 Training Credits
Advanced Registration
$800
Advanced Registration
8 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

1 Day

Who should attend:

FPGA designers, logic designers, and anyone who needs an in-depth knowledge of the PCI Express protocol

Prerequisites

None

Software Tools

None requiredVCD viewer optional

Hardware

Array

Last Updated: 2019-06-06_1626