Xilinx Training Courses
ACAP Courses
- Designing with the Versal™ ACAP: Architecture and Methodology
This course helps you to learn about Versal™ ACAP architecture and design methodology.
The emphasis of this course is on reviewing the architecture of the Versal™ ACAP, describing the different engines available in the Versal™ architecture and what resources they contain, utilizing the hardened blocks available in the Versal™ architecture, using the design tools and methodology provided by Xilinx to create complex systems, describing the network on chip (NoC) and AI Engine concepts and their architectures, and performing system-level simulation and debugging.
- Designing with the Versal™ ACAP: Network on Chip
This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal™ device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on enumerating the major components comprising the NoC architecture in the Versal™ ACAP, implementing a basic design using the NoC, and configuring the NoC for efficient data movement.
- Designing with Versal™ AI Engine 1
This course describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to utilize the AI Engine library for faster development.
The emphasis of this course is on illustrating the AI Engine architecture, designing single AI Engine kernels, designing multiple AI kernels using data flow graphs with the Vitis™ IDE, reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL), and analyzing and debugging kernel performance.
- Designing with Versal™ AI Engine 2
This course describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade stream, buffer location constraints, run-time parameterization and APIs to update and/read run-time parameters.
The emphasis of this course is on implementing a system-level design flow (PS + PL + AIE) and the supported simulation, using an interface for data movement between the PL and AI Engine, utilizing advanced MAC intrinsics to implement filters, utilizing the AI Engine library for faster development, and applying advanced features for optimizing a system-level design.
- Designing with Versal™ AI Engine 3
This course covers the advanced features of the Versal™ ACAP AI Engine, including debugging an application in the Vitis™ unified software platform, using filter intrinsics, implementing a system design in hardware, and optimizing an AI Engine kernel program.
The emphasis of this course is on describing the advanced features of the Versal™ ACAP AI Engine architecture, debugging applications using the Vitis™ unified software platform, using AI Engine filter intrinsics and programming a FIR filter using filter intrinsics, implementing system integration in hardware, and optimizing AI Engine kernels using compiler directives, programming style, and efficient movement of data.
AI Courses
- Accelerating Applications with the Vitis™ Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications. Also learn how to run designs on the Xilinx Alveo™ accelerator card using Nimbix Cloud.
- Developing AI Inference Solutions with the Vitis™ AI Platform
This course describes how to use the Vitis™ AI development platform in conjunction with DNN algorithms, models, inference and training, and frameworks on cloud and edge computing platforms.
System Courses
- Migrating to the Vitis™ Embedded Software Development IDE Workshop
This workshop demonstrates the tools and techniques required for software design and development using the Vitis™ unified software platform.
- Zynq® All Programmable SoC System Architecture
The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq® All Programmable SoC.
This course presents the features and benefits of the Zynq® architecture for making decisions on how to best architect a Zynq® All Programmable SoC project. It covers the architecture of the ARM™ Cortex®-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq® All Programmable SoC.
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
- Zynq® UltraScale+™ MPSoC for the System Architect
This two-day course is structured to provide system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.
Special Events
- Vitis™ FastTrack Series
BLT's Vitis™ FastTrack series demonstrates the tools and techniques required for both software and hardware accelerated design using the Vitis™ Unified Software platform.
Learn how Vitis™ helps accelerate C, C++, and AI applications for cloud, edge, and embedded designs in a single suite. Learn how to migrate existing SDK projects and develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both embedded and cloud applications.
- Vitis™ FastTrack: Session 1 - Essential Overview
BLT's Vitis™ FastTrack series demonstrates the tools and techniques required for both software and hardware accelerated design using the Vitis™ Unified Software platform.
Learn how Vitis™ helps accelerate C, C++, and AI applications for cloud, edge, and embedded designs in a single suite. Learn how to migrate existing SDK projects and develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both embedded and cloud applications.
- Vitis™ FastTrack: Session 2 - AI
BLT's Vitis™ FastTrack series demonstrates the tools and techniques required for both software and hardware accelerated design using the Vitis™ Unified Software platform.
Learn how Vitis™ helps accelerate C, C++, and AI applications for cloud, edge, and embedded designs in a single suite. Learn how to migrate existing SDK projects and develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both embedded and cloud applications.
- Vitis™ FastTrack: Session 3 - System Debug
BLT's Vitis™ FastTrack series demonstrates the tools and techniques required for both software and hardware accelerated design using the Vitis™ Unified Software platform.
Learn how Vitis™ helps accelerate C, C++, and AI applications for cloud, edge, and embedded designs in a single suite. Learn how to migrate existing SDK projects and develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both embedded and cloud applications.
- Designing with the Zynq® UltraScale+™ RFSoC
This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.
The focus is on:
- Describing the RFSoC family in general
- Identifying applications for the Data Converter and SD-FEC blocks
- Configuring, simulating, and implementing the blocks
- Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes
- Identifying proper layout and PCB considerations since the Zynq® UltraScale+™ RFSoC is both a high-speed and an analog and digital device
- Xilinx for Managers
Managers of Xilinx-based programs are under pressure to produce quality results and don't have time to reinvent the wheel or deal with avoidable problems. Recognizing and mitigating risk, knowing how to accelerate schedules, along with handling issues and additional costs, are all facets that can make or break a project... especially with new or challenging technologies.
Xilinx for Managers addresses these issues. BLT has been involved with hundreds of FPGA/SoC designs in over three decades and has directed the efforts of hundreds of engineers. We'll teach you how to accelerate your projects and turn the mystery of FPGA/SoCs into a straightforward discipline.
While BLT's other courses are targeted at hard-core engineers, expanding and deepening their knowledge, this course offers a management perspective.
For Xilinx-based projects, management's commitment to methodology is essential to a project's schedule or budget. With the right knowledge, as a manager, you can really make a difference.
- Request a Custom or Private Course
Custom and Private classes can be created and/or delivered to your team at your location or in a nearby facility.
Benefits of custom and private classes include:
- Reduced travel time and costs
- Ability to control the pace of the class
- Ability to control the content of the class
- Exclusive access to a Xilinx instructor
- Opportunity to more openly discuss issues with your peers
- Ability to discuss confidential issues (BLT under NDA)
Custom Classes
Classes may also be customized to meet your special requirements.
Turnaround Time
It may take up to one month from the time this request is received to the date of the actual class, but we will get your class on the schedule as soon as possible.
If your class request is for an on-site class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.
Boot Camps
- Vivado™ Boot Camp: Basic Training
Vivado™ Boot Camp: Basic Training, is targeted towards engineers with little to no Xilinx knowledge or experience. It provides a fundamental understanding of Xilinx Silicon and Software.
Topics covered include device application areas and overviews of Xilinx silicon and Vivado™ tools.
- Vivado™ Boot Camp Phase-1: Designing for Performance
This course focuses on understanding as well as how to properly design for the primary resources found in the 7 Series FPGA. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also introduces the UltraScale, UltraScale+™ architectures and Versal™. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.
In addition, you will learn how to best migrate your design and IP to the UltraScale™ architecture and the best way to use the Vivado™ Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
- Vivado™ Boot Camp Phase-2: Implementing for Performance
This course helps in designing an FPGA design, which includes creating a Vivado™ Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing and debugging the design. You will also build an effective FPGA design using synchronous design techniques, using the Vivado™ IP integrator to create a sub-system and using proper HDL coding techniques to improve design performance.
- Vivado™ Boot Camp Phase-3: Achieving Performance
This course examines advanced timing constraints and exceptions. It demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, floorplanning and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado™ Logic Analyzer.
- Embedded Systems Hardware Design Boot Camp
This course is designed to bring FPGA designers up to speed developing embedded systems using the Vivado™ Design Suite. The features and capabilities of the Zynq® UltraScale+™ MPSoC and the Zynq®-7000 SoC are covered in lectures, demonstrations and labs, along with general embedded concepts, tools and techniques. Additionally, advanced embedded topics included in this course cover the implementation of level 1 and level 2 device drivers, Asynchronous Multiprocessing (AMP), and Xilinx's embedded operating system, PetaLinux. The hands-on labs utilizing actual Xilinx ZCU104 Evaluation Boards provide students with experience designing, expanding and modifying an embedded system, including booting techniques and hardware-software co-debugging.
This is an advanced class. Those not meeting the prerequisites will struggle.
Languages Courses
- Designing with VHDL
This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
In this three-day course, you will gain valuable hands-on experience.
- Advanced VHDL
Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.
The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.
- Designing with Verilog
This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.
In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. - Designing with SystemVerilog
This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs. - Verification with SystemVerilog
This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs.
Hardware Courses
- C-based Design: High-Level Synthesis with the Vivado™ HLx Tool
The course provides a thorough introduction to the Vivado™ High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado™ HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.
- Advanced Features and Techniques of Embedded Systems Design
Advanced Features and Techniques of Embedded Systems Design provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Vivado™ IP Integrator. This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq® All Programmable System on a Chip (SoC) or MicroBlaze® soft processor.
This course builds on the skills gained in the Embedded Systems Design course. Labs provide hands-on experience with developing, debugging, and simulating an embedded system. Utilizing memory resources and implementing high-performance DMA are also covered. Labs use demo boards in which designs are downloaded and verified.
- Embedded Systems Design
This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado™ Design Suite. The features and capabilities of both the Zynq® All Programmable System on a Chip (SoC) and the MicroBlaze® soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.
The Xilinx Zynq® All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.
- Designing with the Xilinx 7 Series Families
Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Vivado™ Boot Camp: Basic Training course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.
Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
- Designing with the UltraScale™ and UltraScale+™ Architectures
This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ and UltraScale+™ architectures. Targeted towards designers who have used the Vivado™ Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families.
Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.
In addition, you will learn how to best migrate your design and IP to the UltraScale™ architecture and the best way to use the Vivado™ Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
Software Courses
- C-based Design: High-Level Synthesis with the Vivado™ HLx Tool
The course provides a thorough introduction to the Vivado™ High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado™ HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.
- Advanced SDSoC® Development Environment and Methodology
This two-day course is structured to help designers employ SDSoC® development environment optimization techniques to create high-performance, accelerated systems. The focus is on optimizing memory access and hardware functions, generating C-callable IP libraries, and creating custom platforms. The course also includes an introduction to the Xilinx reVISION Stack.
- Developing and Optimizing Applications Using the OpenCL Framework for FPGAs
Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel development environment for use on Xilinx FPGAs. Porting existing applications is also covered.
This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources.
- Embedded Design with PetaLinux Tools
This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded Linux system targeting a Zynq® All Programmable System on a Chip (SoC) processor and Zynq® UltraScale+™ MPSoC processor development board using PetaLinux Tools. The course offers students hands-on experience with building the environment and booting the system using a Zynq® All Programmable SoC or Zynq® UltraScale+™ MPSoC design with PetaLinux Tools on the ARM™ Cortex®-A9 or Cortex®-A53 processor.
This course also introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow.
- Embedded Systems Software Design
This two-day course introduces you to software design and development for the Xilinx Zynq® All Programmable System on a Chip (SoC) using the Xilinx Software Development Kit (SDK). You will learn the concepts, tools, and techniques required for the software phase of the design cycle.
Topics are comprehensive, covering the basics of SDK tool use, customization of the board support packages (BSPs) for resource access and management of the Xilinx Standalone library. Major topics include device driver use, user application debugging and integration.
Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. Sufficient practical information is provided to start developing software applications for the ARM™ Cortex®-A9 and MicroBlaze® processors.
Additionally, this course covers developing software applications for a Xilinx embedded system based on a MicroBlaze® processor.
- Zynq® UltraScale+™ MPSoC for the Software Developer
This two-day course is structured to provide software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq® UltraScale+™ MPSoC family.
System Courses
- Migrating to the Vitis™ Embedded Software Development IDE Workshop
This workshop demonstrates the tools and techniques required for software design and development using the Vitis™ unified software platform.
- Zynq® All Programmable SoC System Architecture
The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq® All Programmable SoC.
This course presents the features and benefits of the Zynq® architecture for making decisions on how to best architect a Zynq® All Programmable SoC project. It covers the architecture of the ARM™ Cortex®-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq® All Programmable SoC.
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
- Zynq® UltraScale+™ MPSoC for the System Architect
This two-day course is structured to provide system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.
FPGA Courses
- Xilinx Partial Reconfiguration Tools & Techniques
This course demonstrates how to use the Vivado™ Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.
This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.
- UltraFast® Design Methodology
This course describes the FPGA design best practices and skills to be successful using the Vivado™ Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado™ software. This course encapsulates this information with an UltraFast® design methodology case study. The UltraFast® design methodology checklist is also introduced.
- Designing with the Xilinx 7 Series Families
Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Vivado™ Boot Camp: Basic Training course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.
Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
- Designing with the UltraScale™ and UltraScale+™ Architectures
This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ and UltraScale+™ architectures. Targeted towards designers who have used the Vivado™ Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families.
Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.
In addition, you will learn how to best migrate your design and IP to the UltraScale™ architecture and the best way to use the Vivado™ Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
- Designing FPGAs Using the Vivado™ Design Suite 1
This course offers introductory training on the Vivado™ Design Suite and helps you to understand the FPGA design flow.
For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado™ Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.
- Designing FPGAs Using the Vivado™ Design Suite 2
This course shows you how to build an effective FPGA design using synchronous design techniques, using the Vivado™ IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.
- Designing FPGAs Using the Vivado™ Design Suite 3
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado™ logic analyzer.
- Designing FPGAs Using the Vivado™ Design Suite 4
This course tackles the most sophisticated aspects of the Vivado™ Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado™ Design Suite to achieve design closure.
- Vivado™ Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users
This course will update experienced ISE software users to utilize the Vivado™ Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado™ timing engine. Finally, you will learn about the scripting environment of the Vivado™ Design Suite and how to use the project-based scripting flow.
You will also learn the FPGA design best practices and skills to be successful using the Vivado™ Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado™ software. This course encapsulates this information with an UltraFast® design methodology case study. The UltraFast® design methodology checklist is also introduced.
- Vivado™ Design Suite for ISE Software Project Navigator Users
This course offers introductory training on the Vivado™ Design Suite. This course is for experienced ISE software users who want to take full advantage of the Vivado™ Design Suite feature set. Learn about the Vivado™ Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.
- Designing with the Spartan-6 and Virtex-6 FPGA Families
Are you interested in learning how to effectively utilize Spartan-6 or Virtex-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Vivado™ Boot Camp: Basic Training course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express technology, and GTP transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
Note: A two-day Spartan-6 family only course or two-day Virtex-6 family only course is also available.
SoC & MPSoC Courses
- Embedded Systems Hardware Design Boot Camp
This course is designed to bring FPGA designers up to speed developing embedded systems using the Vivado™ Design Suite. The features and capabilities of the Zynq® UltraScale+™ MPSoC and the Zynq®-7000 SoC are covered in lectures, demonstrations and labs, along with general embedded concepts, tools and techniques. Additionally, advanced embedded topics included in this course cover the implementation of level 1 and level 2 device drivers, Asynchronous Multiprocessing (AMP), and Xilinx's embedded operating system, PetaLinux. The hands-on labs utilizing actual Xilinx ZCU104 Evaluation Boards provide students with experience designing, expanding and modifying an embedded system, including booting techniques and hardware-software co-debugging.
- Zynq® All Programmable SoC System Architecture
The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq® All Programmable SoC.
This course presents the features and benefits of the Zynq® architecture for making decisions on how to best architect a Zynq® All Programmable SoC project. It covers the architecture of the ARM™ Cortex®-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq® All Programmable SoC.
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
- Embedded Systems Design
This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado™ Design Suite. The features and capabilities of both the Zynq® All Programmable System on a Chip (SoC) and the MicroBlaze® soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.
The Xilinx Zynq® All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.
- Advanced Features and Techniques of Embedded Systems Design
Advanced Features and Techniques of Embedded Systems Design provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Vivado™ IP Integrator. This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq® All Programmable System on a Chip (SoC) or MicroBlaze® soft processor.
This course builds on the skills gained in the Embedded Systems Design course. Labs provide hands-on experience with developing, debugging, and simulating an embedded system. Utilizing memory resources and implementing high-performance DMA are also covered. Labs use demo boards in which designs are downloaded and verified.
- Zynq® UltraScale+™ MPSoC for the System Architect
This two-day course is structured to provide system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.
- Zynq® UltraScale+™ MPSoC for the Software Developer
This two-day course is structured to provide software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq® UltraScale+™ MPSoC family.
- C-based Design: High-Level Synthesis with the Vivado™ HLx Tool
The course provides a thorough introduction to the Vivado™ High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado™ HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.
- Embedded Systems Software Design
This two-day course introduces you to software design and development for the Xilinx Zynq® All Programmable System on a Chip (SoC) using the Xilinx Software Development Kit (SDK). You will learn the concepts, tools, and techniques required for the software phase of the design cycle.
Topics are comprehensive, covering the basics of SDK tool use, customization of the board support packages (BSPs) for resource access and management of the Xilinx Standalone library. Major topics include device driver use, user application debugging and integration.
Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. Sufficient practical information is provided to start developing software applications for the ARM™ Cortex®-A9 and MicroBlaze® processors.
Additionally, this course covers developing software applications for a Xilinx embedded system based on a MicroBlaze® processor.
- Embedded Design with PetaLinux Tools
This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded Linux system targeting a Zynq® All Programmable System on a Chip (SoC) processor and Zynq® UltraScale+™ MPSoC processor development board using PetaLinux Tools. The course offers students hands-on experience with building the environment and booting the system using a Zynq® All Programmable SoC or Zynq® UltraScale+™ MPSoC design with PetaLinux Tools on the ARM™ Cortex®-A9 or Cortex®-A53 processor.
This course also introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow.
Connectivity Courses
- Designing with Ethernet MAC Controllers
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements. Become familiar with Ethernet IP core design architectures, core IP port naming conventions, and signal waveforms.
- Designing with UltraScale™ FPGA Transceivers
Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale™ FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
- How to Design a High-Speed Memory Interface
This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.
Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.
The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex-7 FPGA KC705 board.
- Designing an Integrated PCI Express System
Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.
- PCIe Protocol Overview
This course focuses on the fundamentals of the PCI Express protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.
Implementation issues are covered in the two-day Designing an Integrated PCI Express System course.
- Signal Integrity and Board Design for Xilinx FPGAs
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
- Designing with Xilinx Serial Transcievers
In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale, UltraScale+™ FPGA or Zynq® UltraScale+™ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.
DSP Courses
- Essential DSP Implementation Techniques for Xilinx FPGAs
This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.
- DSP Design Using System Generator
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.