Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

This course contains modules from these AMD Vivado courses:

COURSE CODE: BLT-VIVB1

This Vivado Boot Camp course for FPGA users focuses on understanding as well as how to properly design for the primary resources found in the AMD 7 Series, UltraScale and Versal FPGAs. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced.

This course also introduces the UltraScale, UltraScale+ architectures and Versal. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the AMD Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

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Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with AMD FPGAs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series and UltraScale FPGAs
  • Specify the CLB resources and the available slice configurations for the 7 series FPGAs
  • Describe the new CLB capabilities of the UltraScale FPGA and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO and DSP resources available for the 7 series and UltraScale FPGAs
  • Describe the UltraRAM features available for the UltraScale FPGAs
  • Properly design for the I/O block and SERDES resources available for the 7 series and UltraScale FPGAs
  • Identify the MMCM, PLL and clock routing resources included with these families
  • Identify the hard resources available for implementing high performance DDR3/DDR4 physical layer interfaces
  • Describe the additional dedicated hardware for all the 7 series family members
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1Day 2Day 3
  • 7 Series Overview
  • Introduction to UltraScale Architecture
  • CLB Architecture
  • UltraScale Architecture CLB Resources
  • Slice Flip-Flops
  • LAB: CLB Resources
  • LAB: UltraScale Architecture CLB Resources
  • Memory Resources
  • UltraRAM Memory
  • LAB: Memory Resources
  • LAB: UltraRAM Memory
  • DSP Resources
  • UltraScale FPGA DSP Resources
  • LAB: DSP Resources
  • I/O Resources
  • LAB: I/O Resources
  • I/O Resources – Component Mode
  • I/O Resources – Native Mode
  • LAB: I/O Resources – Component Mode
  • LAB: I/O Resources – Native Mode
  • Clocking Resources
  • LAB: Clocking Resources
  • UltraScale Clocking Resources
  • LAB: UltraScale Architecture Clocking Resources
  • Dedicated Hardware
  • UltraScale Transceivers
  • UltraScale Transceivers Wizard
  • Introduction to UltraScale+ Families
  • LAB: Transceivers Wizard
  • Design Migration Methodology
  • LAB: 10G PCS/PMA and MAC Design Migration
  • Zynq® All Programmable SoC Overview
  • Zynq UltraScale+ MPSoC: Architectural Overview
  • Versal ACAPs compared to UltraScale+ Devices

Please note: The instructor may change the content order to provide a better learning experience.

Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.