Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO
Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO
This course contains modules from these Xilinx® Vivado® courses:
- Designing FPGAs with the Vivado Design Suite 1
- Designing FPGAs with the Vivado Design Suite 2
- Designing with the UltraScale and UltraScale+ Architectures
This Vivado Boot Camp course for FPGA users focuses on understanding as well as how to properly design for the primary resources found in the Xilinx 7 Series, UltraScale™ and Versal® FPGAs. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also introduces the UltraScale, UltraScale+™ architectures and Versal. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.
In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Xilinx Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
| 3-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $299/day | $897 | 9 |
| In-Person Registration - $399/day | $1197 | 12 |
| Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
| Private Training | Contact Us | Contact Us |
| Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
The BLT Adaptive Computing Summit
Emerging Solutions for Outer Space, Undersea, and Everywhere in Between
April 25: Columbia, MD • May 2: Melbourne, FL • May 4: Orlando, FL • May 17: Huntsville, AL
Who should attend:
Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with Xilinx FPGAs.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series and UltraScale FPGAs
- Specify the CLB resources and the available slice configurations for the 7 series FPGAs
- Describe the new CLB capabilities of the UltraScale FPGA and the impact that they make on your HDL coding style
- Define the block RAM, FIFO and DSP resources available for the 7 series and UltraScale FPGAs
- Describe the UltraRAM features available for the UltraScale FPGAs
- Properly design for the I/O block and SERDES resources available for the 7 series and UltraScale FPGAs
- Identify the MMCM, PLL and clock routing resources included with these families
- Identify the hard resources available for implementing high performance DDR3/DDR4 physical layer interfaces
- Describe the additional dedicated hardware for all the 7 series family members
- Effectively migrate your IP and design to the UltraScale architecture as quickly as possible
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Working HDL knowledge (VHDL or Verilog)
- Digital design experience