Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO

This course contains modules from these Xilinx® Vivado® courses:

This Vivado Boot Camp course for FPGA users focuses on understanding as well as how to properly design for the primary resources found in the Xilinx 7 Series, UltraScale™ and Versal® FPGAs. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced.

This course also introduces the UltraScale, UltraScale+™ architectures and Versal. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Xilinx Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$8979
In-Person Registration - $399/day$119712
Printed Course Book (A PDF book is included in the course fee)$1001
Private TrainingContact UsContact Us
Follow on CoachingContact UsContact Us

Scheduled Classes

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

Be the first to know. Sign up for our newsletter.

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with Xilinx FPGAs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series and UltraScale FPGAs
  • Specify the CLB resources and the available slice configurations for the 7 series FPGAs
  • Describe the new CLB capabilities of the UltraScale FPGA and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO and DSP resources available for the 7 series and UltraScale FPGAs
  • Describe the UltraRAM features available for the UltraScale FPGAs
  • Properly design for the I/O block and SERDES resources available for the 7 series and UltraScale FPGAs
  • Identify the MMCM, PLL and clock routing resources included with these families
  • Identify the hard resources available for implementing high performance DDR3/DDR4 physical layer interfaces
  • Describe the additional dedicated hardware for all the 7 series family members
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1Day 2Day 3
  • 7 Series Overview
  • Introduction to UltraScale Architecture
  • CLB Architecture
  • UltraScale Architecture CLB Resources
  • Slice Flip-Flops
  • LAB: CLB Resources
  • LAB: UltraScale Architecture CLB Resources
  • Memory Resources
  • UltraRAM Memory
  • LAB: Memory Resources
  • LAB: UltraRAM Memory
  • DSP Resources
  • UltraScale FPGA DSP Resources
  • LAB: DSP Resources
  • I/O Resources
  • LAB: I/O Resources
  • I/O Resources – Component Mode
  • I/O Resources – Native Mode
  • LAB: I/O Resources – Component Mode
  • LAB: I/O Resources – Native Mode
  • Clocking Resources
  • LAB: Clocking Resources
  • UltraScale Clocking Resources
  • LAB: UltraScale Architecture Clocking Resources
  • Dedicated Hardware
  • UltraScale Transceivers
  • UltraScale Transceivers Wizard
  • Introduction to UltraScale+ Families
  • LAB: Transceivers Wizard
  • Design Migration Methodology
  • LAB: 10G PCS/PMA and MAC Design Migration
  • Zynq® All Programmable SoC Overview
  • Zynq UltraScale+ MPSoC: Architectural Overview
  • Versal ACAPs compared to UltraScale+ Devices

Please note: The instructor may change the content order to provide a better learning experience.

Updated 7-14-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.