Developing and Optimizing Applications Using the OpenCL Framework for FPGAs
Developing and Optimizing Applications Using the OpenCL Framework for FPGAs
DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.
Please contact the BLT Training Team to schedule a private class.
Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel development environment for use on AMD Xilinx FPGAs. Porting existing applications is also covered.
This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources.
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Who should attend:
Software and hardware developers who want to develop OpenCL, C/C++, and RTL applications in the SDAccel development environment.
Skills Gained
After completing this comprehensive training, you will know how to:
- Identify parallel computing applications suitable for accelerating on FPGAs
- Discover how the FPGA architecture lends itself to parallel computing
- Write OpenCL programs for FPGAs
- Examine the OpenCL execution model
- Analyze the OpenCL memory model
- Profile and debug OpenCL code using the SDAccel development environment
- Discover how to maximize performance in FPGA fabric
- Efficiently utilize FPGA memory resources
- Utilize the SDAccel development environment
- Rapidly develop FPGA applications using OpenCL
- Port programs written in OpenCL for CPUs or GPUs to Xilinx FPGAs
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic knowledge of C/C++