Vitis Model Composer: A MATLAB and Simulink-based Product with DSP Techniques

• Architecture
• FPGA Math
• Shift Registers, RAM, and Applications
• FIR Filter
• Advanced Filter Techniques
• Fast Fourier Transform
• Video and Imaging
• Where Do We Go From Here?
• Demonstration: System Generator and the CORE Generator™ Tool with a DSP-Targeted Reference Design
  Targeted Reference Design Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of Xilinx DSP tools and IP. Reinforce the concepts studied in the course material and exercises.
• Where Can I Learn More?

Introduction to Vitis Model Composer

• Introduction to Vitis Model Composer: Introduces the Vitis Model Composer tool and describe the optimized HDL, HLS, and AI Engine library blocks available in Vitis Model Composer. {Lecture}

• Basics of the Simulink Environment: Describes the Simulink software environment, some of the commonly used signal source and sink blocks available in the Simulink software, and how hierarchical designs are created and protected using masked subsystems. {Lecture, Lab}

Vitis Model Composer for HDL

• HDL Library in Vitis Model Composer: Illustrates how the HDL library can be used in Vitis Model Composer and how to analyze performance and resource usage in Vitis Model Composer. {Lecture, Lab}

• HDL Library Compilation and Hardware Co-Simulation: Covers how to import HDL modules as well as perform HDL co-simulation and hardware verification. Reviews the compilation types for Vitis Model Composer designs. Also introduces Super Sample Rate (SSR) blocks in Vitis Model Composer. {Lecture}

• DSP Blocks in Vitis Model Composer: Describes the DSP blocks in the HDL and AI Engine library. Also reviews the basics of AXI4 interfaces. {Lecture, Lab}

• Working with Filter Designs: Describes the concept of designing filters supported by Vitis Model Composer. {Lecture, Lab}

• Working with Multi-Rate Systems: Explains how a multi-rate DSP system uses multiple sampling rates within a system. {Lecture}

Vitis Model Composer for HLS

• HLS Library in Vitis Model Composer: Describes how create Vitis Model Composer designs using HLS block libraries, import C/C++ code into Vitis Model Composer, and generate output products using automatic code generation. {Lecture, Labs}

Vitis Model Composer for AI Engines

• AI Engine Library in Vitis Model Composer: Demonstrates the usage the AI Engine library in Vitis Model composer for creating an AI Engine design, which involves preparing the kernel and importing the AI Engine code as a block. {Lecture}

• AI Engine Simulation and Code Generation: Illustrates the process of generating AI Engine code with a data flow graph, which involves Simulink simulation with the AI Engine library for functional verification. Also describe the hardware validation flow through generating a hardware image targeting a specific platform for the Simulink environment. {Lecture, Labs}

• Connecting AI Engine and Non-AI Engine Blocks: Explains how to interconnect AI Engine blocks and non-AI Engine (HDL and HLS) blocks. {Lecture}

• Debugging an AI Engine Design in Vitis Model Composer: Shows how to use the Vitis analyzer for viewing and analyzing various parameters that are useful for debugging Versal AI Engines. {Lecture, Lab}

GitHub Examples

• Exploring Vitis Model Composer Examples in GitHub: Introduces different categories of Vitis Model Composer examples in GitHub and describes the methods to access these examples from GitHub. {Lecture}