Vitis Model Composer: A MATLAB and Simulink-based Product with DSP Techniques

Included in this course are core modules from our class Essential DSP Implementation Techniques for AMD FPGAs.

COURSE CODE: DSP-MCSIM

This course provides experience with using the AMD Vitis Model Composer tool for model-based designs.

The course provides experience with:

  • Creating a model-based design using HDL, HLS, and AI Engine library blocks along with custom blocks in Vitis Model Composer
  • Implementing DSP functions using Vitis Model Composer
  • Utilizing design implementation tools
  • Transforming algorithmic specifications to production-quality IP implementations using automatic optimizations and leveraging the high-level synthesis technology of the Vitis HLS tool
  • Creating Versal AI Engine graphs and kernels using Vitis Model Composer
  • Connecting AI Engine blocks and non-AI Engine blocks
  • Verifying and debugging AI Engine code using the Vitis analyzer
  • Simulating and debugging a complex system created using AI Engine library blocks
  • Performing hardware validation using Vitis Model Composer
  • Reviewing basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing
  • Exploring a variety of filter techniques with a focus on optimal implementation in AMD devices and continues with an examination of FFTs, video, and image processing.
  • Introducing AMD cores and IP that are relevant to signal processing

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

Live Online Training (9am-5pm ET)

Training Duration:

3 Days

Looking for the Vitis Model Composer Workshop?

Click Here.

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Be the first to know. Sign up for our newsletter.

Who should attend:

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL, and HLS algorithms using the MathWorks MATLAB and Simulink software and want to use Vitis Model Composer.

Software Tools

  • Vivado Design Suite
  • Vitis unified software platform
  • Vitis HLS tool
  • MATLAB with Simulink software R2022a

Hardware

  • Architecture: UltraScale+ FPGAs and Versal AI Core series
  • Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

* This course focuses on the UltraScale and Versal architectures

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use optimized HDL, HLS, and AI Engine blocks directly from the Simulink tool library browser
  • Create, simulate, and debug a Vitis Model Composer design in the Simulink environment using HDL, HLS, and AI Engine block libraries
  • Perform co-simulation and hardware verification
  • Use DSP blocks in Vitis Model Composer to implement DSP functions
  • Implement multi-rate systems in Vitis Model Composer
  • Design a processor-controllable interface using Vitis Model Composer
  • Generate IPs from C-based design sources using the Vitis HLS tool for use in the Vitis Model Composer environment
  • Import custom HDL, HLS, and AI Engines code as blocks into Vitis Model Composer
  • Generate output products using automatic code generation
  • Connect AI Engine blocks and non-AI Engine blocks
  • Perform AI Engine code verification using the Vitis analyzer
  • Create, simulate, and debug a complex system created using AI Engine library blocks
  • Validate an AI Engine design using hardware emulation

Course Outline

Day 1Day 2Day 3
Back to Basics
  • Architecture {Lecture}
FPGA Math
  • Shift Registers, RAM, and Applications {Lecture}
  • FIR Filter {Lecture}
  • Advanced Filter Techniques {Lecture}
  • Fast Fourier Transform {Lecture}
  • Video and Imaging {Lecture}
Where Do We Go From Here?
  • System Generator and the CORE Generator Tool with a DSP-Targeted Reference Design {Demo}
Targeted Reference Design
  • Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of AMD DSP tools and IP. Reinforce the concepts studied in the course material and exercises. {Lecture, Lab}

Where Can I Learn More?
Introduction to Vitis Model Composer
  • Introduction to Vitis Model Composer
    Introduces the Vitis Model Composer tool and describe the optimized HDL, HLS, and AI Engine library blocks available in Vitis Model Composer. {Lecture}
  • Basics of the Simulink Environment
    Describes the Simulink software environment, some of the commonly used signal source and sink blocks available in the Simulink software, and how hierarchical designs are created and protected using masked subsystems. {Lecture, Lab}

Vitis Model Composer for HDL

  • HDL Library in Vitis Model Composer
    Illustrates how the HDL library can be used in Vitis Model Composer and how to analyze performance and resource usage in Vitis Model Composer {Lecture, Labs}
  • HDL Library Compilation and Hardware Co-Simulation
    Covers how to import HDL modules as well as perform HDL co-simulation and hardware verification. Reviews the compilation types for Vitis Model Composer designs. Also introduces Super Sample Rate (SSR) blocks in Vitis Model Composer. {Lecture}
  • DSP Blocks in Vitis Model Composer
    Describes the DSP blocks in the HDL and AI Engine library. Also reviews the basics of AXI4 interfaces. {Lecture, Lab}
  • Working with Filter Designs
    Describes the concept of designing filters supported by Vitis Model Composer. {Lecture, Lab}
  • Working with Multi-Rate Systems
    Explains how a multi-rate DSP system uses multiple sampling rates within a system. {Lecture}
Vitis Model Composer for HLS
  • HLS Library in Vitis Model Composer
    Describes how create Vitis Model Composer designs using HLS block libraries, import C/C++ code into Vitis Model Composer, and generate output products using automatic code generation. {Lecture, Labs}

Vitis Model Composer for AI Engines

  • AI Engine Library in Vitis Model Composer
    Demonstrates the usage the AI Engine library in Vitis Model composer for creating an AI Engine design, which involves preparing the kernel and importing the AI Engine code as a block. {Lecture}
  • AI Engine Simulation and Code Generation
    Illustrates the process of generating AI Engine code with a data flow graph, which involves Simulink simulation with the AI Engine library for functional verification. Also describe the hardware validation flow through generating a hardware image targeting a specific platform for the Simulink environment. {Lecture, Labs}
  • Connecting AI Engine and Non-AI Engine Blocks
    Explains how to interconnect AI Engine blocks and non-AI Engine (HDL and HLS) blocks. {Lecture}
  • Analyzing and Debugging an AI Engine Design in Vitis Model Composer
    Shows how to use the Vitis analyzer for viewing and analyzing various parameters that are useful for debugging Versal AI Engines. {Lecture, Lab}

GitHub Examples
  • Exploring Vitis Model Composer
    Examples in GitHub Introduces different categories of Vitis Model Composer examples in GitHub and describes the methods to access these examples from GitHub. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic experience with the MATLAB and Simulink software
  • Basic understanding of DSP designs and sampling theory
  • Comfort with the C/C++ programming language for HLS or AI Engine model designs

RELATED COURSES:

Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.