Vitis Model Composer: A MATLAB and Simulink-based Product with DSP Techniques
Vitis Model Composer: A MATLAB and Simulink-based Product with DSP Techniques
Included in this course are modules from our class Essential DSP Implementation Techniques for Xilinx FPGAs.
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.
Gain in-depth experience with:
- Creating a model-based design using HDL, HLS, and AIE library blocks along with custom blocks in Vitis Model Composer
- Implementing DSP functions using Vitis Model Composer
- Utilizing design implementation tools
- Transforming algorithmic specifications to production-quality IP implementations using automatic optimizations and leveraging the high-level synthesis technology of the Vitis HLS tool
- Creating Versal® AI Engine graphs and kernels using Vitis Model Composer
- Connecting AI Engine blocks and non-AI Engine blocks
- Verifying and debugging AI Engine code using the Vitis analyzer
- Simulating and debugging a complex system created using AI Engine library blocks
This course focuses on the UltraScale and Versal architectures.
3-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $299/day | $897 | 9 |
In-Person Registration - $399/day | $1197 | 12 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
Training Duration:
3 Days
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Who should attend:
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL, and HLS algorithms using the MathWorks MATLAB® and Simulink® software and want to use Vitis Model Composer.
Skills Gained
After completing this comprehensive training, you will know how to:
- Use optimized HDL, HLS, and AI Engine blocks directly from the Simulink tool library browser
- Create, simulate, and debug a Vitis Model Composer design in the Simulink environment using HDL, HLS, and AIE block libraries
- Perform co-simulation and hardware verification
- Use DSP blocks in Vitis Model Composer to implement DSP functions
- Implement multi-rate systems in Vitis Model Composer
- Design a processor-controllable interface using Vitis Model Composer
- Generate IPs from C-based design sources using the Vitis HLS tool for use in the Vitis Model Composer environment
- Import custom HDL, HLS, and AI Engines code as blocks into Vitis Model Composer
- Generate output products using automatic code generation
- Connect AI Engine blocks and non-AI Engine blocks
- Perform AI Engine code verification using the Vitis analyzer
- Create, simulate, and debug a complex system created using AI Engine library blocks
Course Outline
Day 1 | Day 2 | Day 3 |
---|---|---|
Back to Basics
| Introduction to Vitis Model Composer
Vitis Model Composer for HDL
| Vitis Model Composer for HLS
Vitis Model Composer for AI Engines
GitHub Examples
|
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic experience with the MATLAB and Simulink software
- Basic understanding of DSP designs and sampling theory
- Comfort with the C/C++ programming language for HLS or AI Engine model designs
RELATED COURSES:
- Essential DSP Implementation Techniques for Xilinx FPGAs
- High-Level Synthesis with the Vitis HLS Tool
- Designing with Versal AI Engine 1: Architecture and Design Flow
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
- Designing with Versal AI Engine 3: Kernel Programming and Optimization