Vivado Boot Camp for the FPGA 2: Tcl Scripting, IP Creation & Debugging

Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging

This course contains modules from these AMD Xilinx courses:

This course helps in designing an FPGA design, which includes creating an AMD Xilinx Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing and debugging the design. You will also build an effective FPGA design using synchronous design techniques, using the Vivado IP integrator to create a sub-system and using proper HDL coding techniques to improve design performance.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$897	9
In-Person Registration - $399/day	$1197	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

Live Online Training (9am-5pm ET)

November 14-16, 2023 | Register Today

March 26-28, 2024 | Register Today

July 16-18, 2024 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

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Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with AMD Xilinx FPGAs.

Skills Gained

After completing this comprehensive training, you will know how to:

Use the New Project Wizard to create a new Vivado IDE project
Describe the supported design flows of the Vivado IDE
Create a Tcl script to create a project, add sources and implement a design
Use Tcl scripting in project and non-project batch flows to synthesize, implement and generate custom timing reports
Synthesize and implement the HDL design
Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
Generate a DRC report to detect and fix design issues early in the flow
Describe and use the clock resources in a design
Apply clock and I/O timing constraints and perform timing analysis
Use the Vivado IDE I/O Planning layout to perform pin assignments
Employ advanced implementation options, such as incremental compile flow, physical optimization techniques and re-entrant mode as last mile strategies
Use the Vivado IP integrator to create a block design
Create and package your own IP and add to the Vivado IP catalog to reuse

Course Outline

Day 1	Day 2	Day 3
Introduction to Vivado Design Flows Introduction to the TCL Environment LAB: Introduction to the TCL Environment Vivado Design Suite Project-Based Flow LAB: Vivado Design Suite Project-Based Flow Scripting in Vivado Design Suite Project Mode LAB: Scripting in Vivado Design Suite Project Mode Vivado Design Suite Non-Project Mode Scripting in Vivado Design Suite Non-Project Mode LAB: Scripting in Vivado Design Suite Non-Project Mode Debugging and Error Management in TCL Scripting Introduction to the Xilinx TCL Store Demo: Introduction to the Xilinx TCL Store Behavioral Simulation Synthesis and Implementation LAB: Synthesis and Implementation Timing Simulation LAB: Timing Simulation LAB: Vivado Design Rules Checks	Design Analysis Using TCL Commands Demo: Design Analysis Using TCL Commands LAB: Design Analysis Using TCL Commands Incremental Compile Flow LAB: Incremental Compile Flow Physical Optimization LAB: Physical Optimization Introduction to Clock Constraints Demo: Introduction to Clock Constraints LAB: Introduction to Clock Constraints Timing Constraints Editor Timing Constraints Wizard LAB: Timing Constraints Wizard Report Clock Networks Demo: Report Clock Networks Vivado Design Suite I/O Pin Planning LAB: Vivado Design Suite I/O Pin Planning I/O Constraints and Virtual Clocks LAB: I/O Constraints and Virtual Clocks Demo: Basic Design Analysis in the Vivado IDE LAB: Basic Design Analysis in the Vivado IDE	Setup and Hold Timing Analysis Introduction to Vivado Timing Reports Demo: Introduction to Vivado Timing Reports Timing Summary Report Demo: Timing Summary Report Vivado IP Flow Demo: Vivado IP Flow LAB: Vivado IP Flow Creating and Packaging Custom IP LAB: Creating and Packaging Custom IP Using an IP Container Demo: Using an IP Container Designing with IP Integrator Demo: Designing with IP Integrator Case Study: Designing with IP Integrator LAB: Designing with IP Integrator Managing Remote IP LAB: Managing Remote IP

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

RELATED COURSES:

Updated 7-14-2023

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