Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

Our exclusive class contains modules from these AMD courses:

COURSE CODE: BLT-VIVB3

This Vivado Design Suite course examines advanced timing constraints and exceptions. It demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, floorplanning and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado Logic Analyzer.

Learn more about the AMD Vivado Design Suite.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

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Who should attend:

Experienced AMD FPGA designers.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Describe the "baselining" process to gain timing closure on a design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Define a properly constrained design
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Utilize floorplanning techniques to improve design performance
  • Use the Vivado logic analyzer and debug flows to debug a design
  • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
  • Utilize AMD Xilinx security features, bitstream encryption and authentication using AES for design and IP security
  • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1Day 2Day 3
  • Generated Clocks
  • Demo: Generated Clocks
  • Clock Group Constraints
  • Demo: Clock Group Constraints
  • Introduction to Timing Exceptions
  • Demo: Introduction to Timing Exceptions
  • LAB: Introduction to Timing Exceptions
  • Timing Constraints Priority
  • I/O Timing Scenarios
  • Source-Synchronous I/O Timing
  • LAB: Source-Synchronous I/O Timing
  • System-Synchronous I/O Timing
  • Demo: System-Synchronous I/O Timing
  • Report Datasheet
  • Demo: Report Datasheet
  • Report Clock Interaction
  • Demo: Report Clock Interaction
  • Case Analysis
  • Baselining
  • Demo: Baselining
  • LAB: Baselining
  • Xilinx Power Estimator Spreadsheet
  • LAB: Xilinx Power Estimator Spreadsheet
  • Power Analysis and Optimization Using the Vivado Design Suite
  • LAB: Power Analysis and Optimization Using the Vivado Design Suite
  • Dynamic Power Estimation Using the Vivado Power Report
  • LAB: Dynamic Power Estimation Using the Vivado Power Report
  • Introduction to Floorplanning
  • Design Analysis and Floorplanning
  • LAB: Design Analysis and Floorplanning
  • Revision Control Systems in the Vivado Design Suite
  • LAB: Revision Control Systems in the Vivado Design Suite
  • Introduction to the Vivado Logic Analyzer
  • Demo: Introduction to the Vivado Logic Analyzer
  • Debug Cores
  • HDL Instantiation Flow
  • LAB: HDL Instantiation Flow
  • Netlist Insertion Flow
  • LAB: Netlist Insertion Flow
  • Introduction to Triggering
  • Sampling and Capturing Data in Multiple Clock Domains
  • LAB: Sampling and Capturing Data in Multiple Clock Domains
  • Debug Flow in an IP Integrator Design
  • LAB: Debug Flow in an IP Integrator Design
  • Remote Debugging Using the Vivado Logic Analyzer
  • LAB: Remote Debugging Using the Vivado Logic Analyzer
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
  • LAB: Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
  • Trigger and Debug at Device Startup
  • Demo: Trigger and Debug at Device Startup
  • Scripting for a VLA Design
  • LAB: Scripting for a VLA Design
  • Vivado Design Suite ECO Flow
  • LAB: Vivado Design Suite ECO Flow
  • Bitstream Security
  • LAB: Bitstream Security
  • Vivado Design Suite Debug Methodology

Please note: The instructor may change the content order to provide a better learning experience.

Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.