Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure
Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure
Our exclusive class contains modules from these AMD Xilinx® courses:
This Vivado® Design Suite course examines advanced timing constraints and exceptions. It demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, floorplanning and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado Logic Analyzer.
Learn more about the Xilinx Vivado Design Suite.
3-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $299/day | $897 | 9 |
In-Person Registration - $399/day | $1197 | 12 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
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Who should attend:
Experienced Xilinx FPGA designers.
Skills Gained
After completing this comprehensive training, you will know how to:
- Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
- Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
- Describe the “baselining” process to gain timing closure on a design
- Apply baseline constraints to determine if internal timing paths meet design timing objectives
- Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
- Define a properly constrained design
- Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
- Utilize floorplanning techniques to improve design performance
- Use the Vivado logic analyzer and debug flows to debug a design
- Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
- Utilize Xilinx security features, bitstream encryption and authentication using AES for design and IP security
- Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- FPGA design experience
- Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging
- Working VHDL or Verilog knowledge and experience