Vivado Boot Camp for the FPGA User 3: Floorplanning & Advanced Timing Closure

Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure

Our exclusive class contains modules from these AMD Xilinx® courses:

This Vivado® Design Suite course examines advanced timing constraints and exceptions. It demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, floorplanning and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado Logic Analyzer.

Learn more about the Xilinx Vivado Design Suite.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$897	9
In-Person Registration - $399/day	$1197	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

Live Online Training (9am-5pm ET)

December 12-14, 2023 | Register Today

April 16-18, 2024 | Register Today

August 6-8, 2024 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

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Who should attend:

Experienced Xilinx FPGA designers.

Skills Gained

After completing this comprehensive training, you will know how to:

Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
Describe the “baselining” process to gain timing closure on a design
Apply baseline constraints to determine if internal timing paths meet design timing objectives
Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
Define a properly constrained design
Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
Utilize floorplanning techniques to improve design performance
Use the Vivado logic analyzer and debug flows to debug a design
Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
Utilize Xilinx security features, bitstream encryption and authentication using AES for design and IP security
Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1	Day 2	Day 3
Generated Clocks Demo: Generated Clocks Clock Group Constraints Demo: Clock Group Constraints Introduction to Timing Exceptions Demo: Introduction to Timing Exceptions LAB: Introduction to Timing Exceptions Timing Constraints Priority I/O Timing Scenarios Source-Synchronous I/O Timing LAB: Source-Synchronous I/O Timing System-Synchronous I/O Timing Demo: System-Synchronous I/O Timing Report Datasheet Demo: Report Datasheet Report Clock Interaction Demo: Report Clock Interaction Case Analysis Baselining Demo: Baselining LAB: Baselining	Xilinx Power Estimator Spreadsheet LAB: Xilinx Power Estimator Spreadsheet Power Analysis and Optimization Using the Vivado Design Suite LAB: Power Analysis and Optimization Using the Vivado Design Suite Dynamic Power Estimation Using the Vivado Power Report LAB: Dynamic Power Estimation Using the Vivado Power Report Introduction to Floorplanning Design Analysis and Floorplanning LAB: Design Analysis and Floorplanning Revision Control Systems in the Vivado Design Suite LAB: Revision Control Systems in the Vivado Design Suite Introduction to the Vivado Logic Analyzer Demo: Introduction to the Vivado Logic Analyzer Debug Cores HDL Instantiation Flow LAB: HDL Instantiation Flow Netlist Insertion Flow LAB: Netlist Insertion Flow	Introduction to Triggering Sampling and Capturing Data in Multiple Clock Domains LAB: Sampling and Capturing Data in Multiple Clock Domains Debug Flow in an IP Integrator Design LAB: Debug Flow in an IP Integrator Design Remote Debugging Using the Vivado Logic Analyzer LAB: Remote Debugging Using the Vivado Logic Analyzer Trigger Using the Trigger State Machine in the Vivado Logic Analyzer LAB: Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Trigger and Debug at Device Startup Demo: Trigger and Debug at Device Startup Scripting for a VLA Design LAB: Scripting for a VLA Design Vivado Design Suite ECO Flow LAB: Vivado Design Suite ECO Flow Bitstream Security LAB: Bitstream Security Vivado Design Suite Debug Methodology

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

FPGA design experience
Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging
Working VHDL or Verilog knowledge and experience

RELATED COURSES:

Updated 7-14-2023

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