$299/Day - Designing FPGAs Using the Vivado Design Suite 3

Designing FPGAs Using the Vivado Design Suite 3

BLT offers Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging and Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure which contain modules from this course.

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (mailed to you)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

See available dates for Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging

Training Duration:

2 Days

We update our schedule regularly. Stay informed.

NEWSLETTER SIGNUP

Who should attend:

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite.

Skills Gained

After completing this comprehensive training, you will know how to:

Employ good alternative design practices to improve design reliability
Define a properly constrained design
Apply baseline constraints to determine if internal timing paths meet design timing objectives
Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
Increase performance by utilizing FPGA design techniques
Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report

Course Outline

Day 1	Day 2
UltraFast^™ Design Methodology: Design Closure Introduces the methodology guidelines covered in this course. Vivado Design Suite Non-Project Mode Create a design in the Vivado Design Suite non-project mode. Baselining Use Xilinx-recommended baselining procedures to progressively meet timing closure. Pipelining Use pipelining to improve design performance. Inference Infer Xilinx dedicated hardware resources by writing appropriate HDL code. Revision Control Systems in the Vivado Design Suite Use version control systems with Vivado design flows. Timing Simulation Simulate the design post-implementation to verify that a design works properly on hardware. Synchronization Circuits Use synchronization circuits for clock domain crossings. Report Clock Interaction Use the clock interaction report to identify interactions between clock domains.	Report Datasheet Use the datasheet report to find the optimal setup and hold margin for an I/O interface. Dynamic Power Estimation Using Vivado Report Power Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design. Configuration Modes Understand various configuration modes and select the suitable mode for a design. JTAG to AXI Master Core Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware. Debug Flow in an IP Integrator Block Design Insert the debug cores into IP integrator block designs. Remote Debugging Using the Vivado Logic Analyzer Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location. Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer. Introduction to the Xilinx Tcl Store Introduces the Xilinx Tcl Store. Manipulating Design Properties Using Tcl Query your design and make pin assignments by using various Tcl commands.

Day 1

Day 2

UltraFast^™ Design Methodology: Design Closure
Introduces the methodology guidelines covered in this course.
Vivado Design Suite Non-Project Mode
Create a design in the Vivado Design Suite non-project mode.
Baselining
Use Xilinx-recommended baselining procedures to progressively meet timing closure.
Pipelining
Use pipelining to improve design performance.
Inference
Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
Revision Control Systems in the Vivado Design Suite
Use version control systems with Vivado design flows.
Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware.
Synchronization Circuits
Use synchronization circuits for clock domain crossings.
Report Clock Interaction
Use the clock interaction report to identify interactions between clock domains.

Report Datasheet
Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
Dynamic Power Estimation Using Vivado Report Power
Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
Configuration Modes
Understand various configuration modes and select the suitable mode for a design.
JTAG to AXI Master Core
Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.
Debug Flow in an IP Integrator Block Design
Insert the debug cores into IP integrator block designs.
Remote Debugging Using the Vivado Logic Analyzer
Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.
Introduction to the Xilinx Tcl Store
Introduces the Xilinx Tcl Store.
Manipulating Design Properties Using Tcl
Query your design and make pin assignments by using various Tcl commands.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Designing FPGAs Using the Vivado Design Suite 1
Designing FPGAs Using the Vivado Design Suite 2
Intermediate HDL knowledge (VHDL or Verilog)
Solid digital design background

RELATED COURSES:

Updated 4-10-22

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