Designing FPGAs Using the Vivado Design Suite 3

Designing FPGAs Using the Vivado Design Suite 3 – Timing Closure, CDC, and Debugging

COURSE CODE: FPGA-VDES3

Learn how to effectively employ timing closure techniques.

This course includes:

Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
Showing optimum HDL coding techniques that help with design timing closure
Illustrating the advanced capabilities of the Vivado logic analyzer. to debug a design

This course builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

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Who should attend:

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite.

Software Tools

Vivado Design Suite

Hardware

Architecture: UltraScale FPGAs*
Demo board: Zynq UltraScale+ ZCU104 board*

* This course focuses on the UltraScale architectures.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Employ good alternative design practices to improve design reliability
Define a properly constrained design
Apply baseline constraints to determine if internal timing paths meet design timing objectives
Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
Perform quality of results (QoR) assessments at different stages to improve the QoR score
Increase performance by utilizing FPGA design techniques
Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
Describe how to enable remote debug

Course Outline

Day 1	Day 2	Day 3
UltraFast Design Methodology (UFDM) UltraFast Design Methodology: Implementation Introduces the methodology guidelines covered in this course. {Lecture} Simulation Timing Simulation Illustrates simulating a design post-implementation to verify that the design works properly on hardware. {Lecture, Lab} Design Techniques Baselining Demonstrates how to use recommended baselining procedures to progressively meet timing closure. {Lecture, Demo, Lab} Pipelining Describes using pipelining to improve design performance. {Lecture, Lab} Inference Outlines how to infer AMD-dedicated hardware resources by writing appropriate HDL code. {Lecture, Lab} Timing – Advanced I/O Timing Scenarios Provides an overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center-aligned data. {Lecture} System-Synchronous I/O Timing Demonstrates applying I/O delay constraints and performing static timing analysis for a system-synchronous input interface. {Lecture, Demo} Source-Synchronous I/O Timing Demonstrates applying I/O delay constraints and performing static timing analysis for a source-synchronous, double data rate (DDR) interface. {Lecture, Lab} Timing Constraints Priority Reviews how to identify the priority of timing constraints. {Lecture}	Design Analysis Report Clock Interaction Describes the clock interaction report, which is used to identify interactions between clock domains. {Lecture, Demo} Report Datasheet Describes the datasheet report, which is used to find the optimal setup and hold margin for an I/O interface. {Lecture, Demo} QoR Reports Overview Discusses what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture} CDC Sampling and Capturing Data in Multiple Clock Domains Provides an overview of debugging a design with multiple clock domains that require multiple ILAs. {Lecture, Lab} Clock Domain Crossing (CDC) and Synchronization Circuits Highlights how to use synchronization circuits for clock domain crossings. {Lecture, Lab} Version Control System Revision Control Systems in the Vivado Design Suite Investigates using version control systems with the Vivado design flows. {Lecture, Lab} Power Dynamic Power Estimation Using Vivado Report Power Describes how to use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.{Lecture, Lab}	Configuration Configuration Modes Reviews the various configuration modes and selecting a suitablemode for a design. {Lecture} Debugging Netlist Insertion Debug Probing Flow Covers the netlist insertion flow for debug using the Vivado logic analyzer. {Lecture, Lab} JTAG to AXI Master Core Describes how this debug core is used to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware. {Lecture, Demo} Debug Flow in an IP Integrator Block Design Shows how to insert the debug cores into IP integrator block designs. {Lecture, Lab} Remote Debugging Using the Vivado Logic Analyzer Demonstrates using the Vivado logic analyzer to configure an FPGA, set up triggering, and view sampled data from a remote location. {Lecture, Lab} Tcl Commands Design Analysis Using Tcl Commands Describes how to analyze a design using Tcl commands. {Lecture, Demo}

Day 1

Day 2

Day 3

UltraFast Design Methodology (UFDM)

UltraFast Design Methodology: Implementation
Introduces the methodology guidelines covered in this course. {Lecture}

Simulation

Timing Simulation
Illustrates simulating a design post-implementation to verify that the design works properly on hardware. {Lecture, Lab}

Design Techniques

Baselining
Demonstrates how to use recommended baselining procedures to progressively meet timing closure. {Lecture, Demo, Lab}
Pipelining
Describes using pipelining to improve design performance. {Lecture, Lab}
Inference
Outlines how to infer AMD-dedicated hardware resources by writing appropriate HDL code. {Lecture, Lab}

Timing – Advanced

I/O Timing Scenarios
Provides an overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center-aligned data. {Lecture}
System-Synchronous I/O Timing
Demonstrates applying I/O delay constraints and performing static timing analysis for a system-synchronous input interface. {Lecture, Demo}
Source-Synchronous I/O Timing
Demonstrates applying I/O delay constraints and performing static timing analysis for a source-synchronous, double data rate (DDR) interface. {Lecture, Lab}
Timing Constraints Priority
Reviews how to identify the priority of timing constraints. {Lecture}

Design Analysis

Report Clock Interaction
Describes the clock interaction report, which is used to identify interactions between clock domains. {Lecture, Demo}
Report Datasheet
Describes the datasheet report, which is used to find the optimal setup and hold margin for an I/O interface. {Lecture, Demo}
QoR Reports Overview
Discusses what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture}

CDC

Sampling and Capturing Data in Multiple Clock Domains
Provides an overview of debugging a design with multiple clock domains that require multiple ILAs. {Lecture, Lab}
Clock Domain Crossing (CDC) and Synchronization Circuits
Highlights how to use synchronization circuits for clock domain crossings. {Lecture, Lab}

Version Control System

Revision Control Systems in the Vivado Design Suite
Investigates using version control systems with the Vivado design flows. {Lecture, Lab}

Power

Dynamic Power Estimation Using Vivado Report Power
Describes how to use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.{Lecture, Lab}

Configuration

Configuration Modes
Reviews the various configuration modes and selecting a suitablemode for a design. {Lecture}

Debugging

Netlist Insertion Debug Probing Flow
Covers the netlist insertion flow for debug using the Vivado logic analyzer. {Lecture, Lab}
JTAG to AXI Master Core
Describes how this debug core is used to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware. {Lecture, Demo}
Debug Flow in an IP Integrator Block Design
Shows how to insert the debug cores into IP integrator block designs. {Lecture, Lab}
Remote Debugging Using the Vivado Logic Analyzer
Demonstrates using the Vivado logic analyzer to configure an FPGA, set up triggering, and view sampled data from a remote location. {Lecture, Lab}

Tcl Commands

Design Analysis Using Tcl Commands
Describes how to analyze a design using Tcl commands. {Lecture, Demo}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Intermediate HDL knowledge (VHDL or Verilog)
Solid digital design background
Designing FPGAs Using the Vivado Design Suite 1 (recommended)
Designing FPGAs Using the Vivado Design Suite 2 (recommended)

RELATED COURSES:

Updated 03-12-2025

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Designing FPGAs Using the Vivado Design Suite 3 – Timing Closure, CDC, and Debugging