Designing FPGAs Using the Vivado™ Design Suite 3
Designing FPGAs Using the Vivado™ Design Suite 3
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado™ logic analyzer.
Skills Gained
After completing this comprehensive training, you will know how to:
- Employ good alternative design practices to improve design reliability
- Define a properly constrained design
- Apply baseline constraints to determine if internal timing paths meet design timing objectives
- Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
- Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
- Increase performance by utilizing FPGA design techniques
- Use Vivado™ Design Suite reports and utilities to full advantage, especially the Clock Interaction report
Course Outline
Day 1
- UltraFast® Design Methodology: Design Closure
Introduces the methodology guidelines covered in this course. - Vivado™ Design Suite Non-Project Mode
Create a design in the Vivado™ Design Suite non-project mode. - Baselining
Use Xilinx-recommended baselining procedures to progressively meet timing closure. - Pipelining
Use pipelining to improve design performance. - Inference
Infer Xilinx dedicated hardware resources by writing appropriate HDL code. - Revision Control Systems in the Vivado™ Design Suite
Use version control systems with Vivado™ design flows. - Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware. - Synchronization Circuits
Use synchronization circuits for clock domain crossings. - Report Clock Interaction
Use the clock interaction report to identify interactions between clock domains.
Day 2
- Report Datasheet
Use the datasheet report to find the optimal setup and hold margin for an I/O interface. - Dynamic Power Estimation Using Vivado™ Report Power
Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design. - Configuration Modes
Understand various configuration modes and select the suitable mode for a design. - JTAG to AXI Master Core
Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware. - Debug Flow in an IP Integrator Block Design
Insert the debug cores into IP integrator block designs. - Remote Debugging Using the Vivado™ Logic Analyzer
Use the Vivado™ logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location. - Trigger Using the Trigger State Machine in the Vivado™ Logic Analyzer
Use trigger state machine code to trigger the ILA and capture data in the Vivado™ logic analyzer. - Introduction to the Xilinx Tcl Store
Introduces the Xilinx Tcl Store. - Manipulating Design Properties Using Tcl
Query your design and make pin assignments by using various Tcl commands.
No Scheduled Sessions – Contact Us to ask about setting one up!
Education Investment Options
Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
REGISTER
Training Duration:
2 Days
Who should attend:
FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado™ Design Suite
Prerequisites:
- Designing FPGAs Using the Vivado™ Design Suite 1
- Designing FPGAs Using the Vivado™ Design Suite 2
- Intermediate HDL knowledge (VHDL or Verilog)
- Solid digital design background
Version: 2021-03-17_0932