Spartan-6 / ISE User Migration Training

This course is designed for the user migrating from a Spartan-6® or the ISE® tool into newer devices and Vivado®.

You’ll learn designing an FPGA in Vivado, including creating a Xilinx® Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing and debugging the design. You will also build an effective FPGA design using synchronous design techniques, using the Vivado IP integrator to create a sub-system and using proper HDL coding techniques to improve design performance.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$8979
In-Person Registration - $399/day$119712
Printed Course Book (A PDF book is included in the course fee)$1001
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Scheduled Classes

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

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Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with either the Spartan-6 or ISE and are migrating their designs to newer devices.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Create a Tcl script to create a project, add sources and implement a design
  • Use Tcl scripting in project and non-project batch flows to synthesize, implement and generate custom timing reports
  • Synthesize and implement the HDL design
  • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
  • Generate a DRC report to detect and fix design issues early in the flow
  • Describe and use the clock resources in a design
  • Apply clock and I/O timing constraints and perform timing analysis
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques and re-entrant mode as last mile strategies
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse

Course Outline

Day 1Day 2Day 3
  • Introduction to Vivado Design Flows
  • Introduction to the TCL Environment
  • LAB: Introduction to the TCL Environment
  • Vivado Design Suite Project-Based Flow
  • LAB: Vivado Design Suite Project-Based Flow
  • Scripting in Vivado Design Suite Project Mode
  • LAB: Scripting in Vivado Design Suite Project Mode
  • Vivado Design Suite Non-Project Mode
  • Scripting in Vivado Design Suite Non-Project Mode
  • LAB: Scripting in Vivado Design Suite Non-Project Mode
  • Debugging and Error Management in TCL Scripting
  • Introduction to the Xilinx TCL Store
  • Demo: Introduction to the Xilinx TCL Store
  • Behavioral Simulation
  • Synthesis and Implementation
  • LAB: Synthesis and Implementation
  • Timing Simulation
  • LAB: Timing Simulation
  • LAB: Vivado Design Rules Checks
  • Design Analysis Using TCL Commands
  • Demo: Design Analysis Using TCL Commands
  • LAB: Design Analysis Using TCL Commands
  • Incremental Compile Flow
  • LAB: Incremental Compile Flow
  • Physical Optimization
  • LAB: Physical Optimization
  • Introduction to Clock Constraints
  • Demo: Introduction to Clock Constraints
  • LAB: Introduction to Clock Constraints
  • Timing Constraints Editor
  • Timing Constraints Wizard
  • LAB: Timing Constraints Wizard
  • Report Clock Networks
  • Demo: Report Clock Networks
  • Vivado Design Suite I/O Pin Planning
  • LAB: Vivado Design Suite I/O Pin Planning
  • I/O Constraints and Virtual Clocks
  • LAB: I/O Constraints and Virtual Clocks
  • Demo: Basic Design Analysis in the Vivado IDE
  • LAB: Basic Design Analysis in the Vivado IDE
  • Setup and Hold Timing Analysis
  • Introduction to Vivado Timing Reports
  • Demo: Introduction to Vivado Timing Reports
  • Timing Summary Report
  • Demo: Timing Summary Report
  • Vivado IP Flow
  • Demo: Vivado IP Flow
  • LAB: Vivado IP Flow
  • Creating and Packaging Custom IP
  • LAB: Creating and Packaging Custom IP
  • Using an IP Container
  • Demo: Using an IP Container
  • Designing with IP Integrator
  • Demo: Designing with IP Integrator
  • Case Study: Designing with IP Integrator
  • LAB: Designing with IP Integrator
  • Managing Remote IP
  • LAB: Managing Remote IP

Please note: The instructor may change the content order to provide a better learning experience.

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

All in all a great experience.

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

Updated 7-10-22
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