Designing with VHDL
Designing with VHDL
COURSE CODE: LANG-VHDL
This course provides a thorough introduction to the VHDL language.
The emphasis is on:
- Writing efficient hardware designs
- Performing high-level HDL simulations
- Employing structural, register transfer level (RTL), and behavioral coding styles
- Targeting AMD devices specifically and FPGA devices in general
- Utilizing best coding practices
Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. In this three-day course, you will gain valuable hands-on experience.
3-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $600/day | $1800 | 18 |
In-Person Public Registration - $600/day | $1800 | 18 |
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration. | $100 | 1 |
Private Training | Learn More | Learn More |
Coaching | Learn More | Learn More |
Scheduled Classes
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Who should attend:
Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.
Software Tools
- Vivado Design Suite
Hardware
- Architecture: N/A*
- Demo board: Zynq UltraScale+ MPSoC ZCU104 board
* This course does not focus on any particular architecture.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Implement the VHDL portion of coding for synthesis
- Identify the differences between behavioral and structural coding styles
- Distinguish coding for synthesis versus coding for simulation
- Use scalar and composite data types to represent information
- Use concurrent and sequential control structure to regulate information flow
- Implement common VHDL constructs (finite state machines [FSMs], RAM/ROM data structures)
- Simulate a basic VHDL design
- Write a VHDL testbench and identify simulation-only constructs
- Identify and implement coding best practices
- Optimize VHDL code to target specific silicon resources within AMD FPGAs and adaptive SoCs
- Create and manage designs within the Vivado Design Suite environment
Course Outline
Day 1 | Day 2 | Day 3 |
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic digital design concepts
- Flip-flops and logic gates
- Basic understanding of synchronous designs