Designing with VHDL

COURSE CODE: LANG-VHDL

This course provides a thorough introduction to the VHDL language.

The emphasis is on:

Writing efficient hardware designs
Performing high-level HDL simulations
Employing structural, register transfer level (RTL), and behavioral coding styles
Targeting AMD devices specifically and FPGA devices in general
Utilizing best coding practices

Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. In this three-day course, you will gain valuable hands-on experience.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$200	2

Scheduled Classes

Live Online Training (Starts at 9am ET)

August 12-14, 2025 | Register Today

December 9-11, 2025 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Be the first to know. Sign up for our newsletter.

Who should attend:

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.

Software Tools

Vivado Design Suite

Hardware

Architecture: N/A*
Demo board: Zynq UltraScale+ MPSoC ZCU104 board

* This course does not focus on any particular architecture.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Implement the VHDL portion of coding for synthesis
Identify the differences between behavioral and structural coding styles
Distinguish coding for synthesis versus coding for simulation
Use scalar and composite data types to represent information
Use concurrent and sequential control structure to regulate information flow
Implement common VHDL constructs (finite state machines [FSMs], RAM/ROM data structures)
Simulate a basic VHDL design
Write a VHDL testbench and identify simulation-only constructs
Identify and implement coding best practices
Optimize VHDL code to target specific silicon resources within AMD FPGAs and adaptive SoCs
Create and manage designs within the Vivado Design Suite environment

Course Outline

Day 1	Day 2	Day 3
Introduction to VHDL Discusses the history of the VHDL language and provides an overview of the different features of VHDL. {Lecture} VHDL Design Units Provides an overview of typical VHDL code, covering design unitssuch as libraries, packages, entities, architectures, and configuration. {Lecture, Lab} VHDL Objects, Keywords, Identifiers Discusses the data objects that are available in the VHDL language as well as keywords and identifiers. {Lecture} Scalar Data Types Covers both intrinsic and commonly used data types. {Lecture} Composite Data Types Covers composite data types (arrays and records). {Lecture} VHDL Operators Reviews all VHDL operator types. {Lecture} Concurrency in VHDL Describes concurrent statements and how signals help in achieving concurrency. {Lecture} Concurrent Assignments Covers both conditional and unconditional assignments. {Lecture, Lab} Processes and Variables Introduces sequential programming techniques for a concurrent language. Variables are also discussed. {Lecture, Demo, Lab}	Control Structures in VHDL: if/else, case Describes conditional statements such as if/else and case statements. {Lecture, Lab} Sequential Looping Statements Introduces the concept of looping in both the simulation and synthesis environments. {Lecture, Lab} Delays in VHDL: wait Statement Covers the wait statement and how it controls the execution of the process statement. {Lecture} Introduction to the VHDL Testbench Introduces the concept of the VHDL testbench to verify the functionality of a design. {Lecture, Lab} VHDL Assert Statements Describes the concept of VHDL assertions. {Lecture} VHDL Attributes Describes attributes, both predefined and user defined. {Lecture} Vivado Simulator Good Coding Practices (VHDL) Discusses the simulation tool and its typical capabilities. {Lecture} VHDL Subprograms Covers the use of subprograms in verification and RTL code to model functional blocks. {Lecture} VHDL Function Describes functions, which are integral to reusable and maintainable code. {Lecture, Lab} VHDL Procedures Describes procedures, common constructs that are also important for reusing and maintaining code. {Lecture}	VHDL Libraries and Packages Demonstrates how libraries and packages are declared and used. {Lecture, Lab} Interacting with Simulation Describes how to interact with a simulation via text I/O. {Lecture} Finite State Machine Overview Provides an overview of finite state machines, one of the more commonly used circuits. {Lecture} Mealy Finite State Machine Describes how to implement a Mealy state machine in which the output is dependent on both the current state and the inputs. {Lecture} Moore Finite State Machine Demonstrates how to implement a Moore state machine in which the output is dependent on the current state only. {Lecture, Lab} FSM Coding Guidelines Describes the guidelines and recommendations for using one o more procedural blocks when coding a finite state machine. {Lecture} Writing a Good Testbench Explores how time-agnostic, self-checking testbenches can be written and applied. {Lecture, Lab} Targeting AMD FPGAs and Adaptive SoCs Focuses on implementation and chip-level optimization specific to AMD devices. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic digital design concepts
- Flip-flops and logic gates
- Basic understanding of synchronous designs

RELATED COURSES:

Updated 03-12-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

Designing with VHDL