Designing with VHDL

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

In this three-day course, you will gain valuable hands-on experience.

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$8979
In-Person Registration - $399/day$119712
Printed Course Book (mailed to you)$1001
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Scheduled Classes

Live Online Training: October 5-7, 2021
Live Online Training: February 15-17, 2022

Training Duration:

3 Days

We update our schedule regularly. Stay informed.

Who should attend:

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Implement the VHDL portion of coding for synthesis
  • Identify the differences between behavioral and structural coding styles
  • Distinguish coding for synthesis versus coding for simulation
  • Use scalar and composite data types to represent information
  • Use concurrent and sequential control structure to regulate information flow
  • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
  • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
  • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the Vivado Design Suite environment

Course Outline

Day 1Day 2Day 3
  • The “Shape” of VHDL
  • Demo: Multiplexer
  • LAB: Using the Tools
  • Data Types
  • Concurrent Operations
  • LAB: Using Concurrent Statements
  • Processes and Variables
  • LAB: Designing a Simple Process
  • Introduction to Testbenches
  • Vivado Simulator Basics
  • LAB: Simulating a Simple Design
  • Creating Memory
  • LAB: Building a Dual-Port Memory
  • Finite State Machines
  • LAB: Building a Moore Finite State Machine
  • Targeting Xilinx FPGAs
  • LAB: Xilinx Tool Flow
  • Loops and Conditional Elaboration
  • LAB: Using Loops
  • Attributes
  • Functions and Procedures
  • Packages and Libraries
  • LAB: Building Your Own Package
  • Interacting with the Simulation
  • Writing a Good Testbench
  • LAB: Building a Meaningful Testbench

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic digital design knowledge

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Updated 9-02-2021