Designing an Integrated PCI Express System with Xilinx Serial Transceivers
Designing an Integrated PCI Express System with Xilinx Serial Transceivers
DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.
COURSE CODE: BLT-MGT-PCIE
Learn how to employ serial transceivers in UltraScale and UltraScale+ FPGA designs or Zynq UltraScale+ MPSoC designs. This class focuses on: Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Utilizing the Transceivers Wizards to instantiate transceiver primitives. Synthesizing and implementing transceiver designs. Taking into account board design as it relates to the transceivers Testing and debugging.
Learn how to implement a Xilinx PCI Express core in custom applications to improve time to market with the PCIe core design. Focus on constructing a Xilinx PCI Express system within the customer education reference design, enumerating various Xilinx PCI Express core products, and identifying the advanced capabilities of the PCIe specification. This course also focuses on the AXI Streaming interconnect.
3-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $600/day | $1800 | 18 |
In-Person Public Registration - $600/day | $1800 | 18 |
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration. | $100 | 1 |
Private Training | Learn More | Learn More |
Coaching | Learn More | Learn More |
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Who should attend:
Hardware designers who want to create applications using Xilinx IP cores for PCI Express Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications.
Skills Gained
After completing this comprehensive training, you will know how to:
- Construct a basic PCIe system by selecting the appropriate core for your application, specifying requirements of an endpoint application, connecting this endpoint with the core, utilizing FPGA resources to support the core, simulating the design
- Identify the advanced capabilities of the PCIe specification protocol and feature set
- Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
- Effectively utilize the following features of the gigabit transceivers: 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding, pre-emphasis and receive equalization
- Use the Transceivers Wizards to instantiate GT primitives in a design
Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design - Use the IBERT design to verify transceiver links on real hardware
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Experience with PCIe specification protocol
- Knowledge of VHDL or Verilog
- Experience with Xilinx implementation tools
- Understanding of Xilinx timing constraints
- Knowledge and experience of Xilinx timing closure
- Experience with a simulation tool, preferably the Vivado simulator
- Moderate digital design experience
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful