Designing an Integrated PCI Express System with Xilinx Serial Transceivers

This exclusive course combines the topics from Designing an Integrated PCI Express System and Designing with Xilinx Serial Transceivers.

Learn how to employ serial transceivers in UltraScale and UltraScale+ FPGA designs or Zynq UltraScale+ MPSoC designs. This focus is on: Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Utilizing the Transceivers Wizards to instantiate transceiver primitives. Synthesizing and implementing transceiver designs. Taking into account board design as it relates to the transceivers Testing and debugging.

Learn how to implement a Xilinx PCI Express core in custom applications to improve time to market with the PCIe core design. The focus is on; constructing a Xilinx PCI Express system within the customer education reference design, enumerating various Xilinx PCI Express core products, and identifying the advanced capabilities of the PCIe specification. This course also focuses on the AXI Streaming interconnect.

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$8979
In-Person Registration - $399/day$119712
Printed Course Book (mailed to you)$1001
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Scheduled Classes

Live Online Training: November 30, 2021 – December 2, 2021
Live Online Training: April 5-7, 2022

Training Duration:

3 Days

We update our schedule regularly. Stay informed.

Who should attend:

Hardware designers who want to create applications using Xilinx IP cores for PCI Express Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Construct a basic PCIe system by selecting the appropriate core for your application, specifying requirements of an endpoint application, connecting this endpoint with the core, utilizing FPGA resources to support the core, simulating the design
  • Identify the advanced capabilities of the PCIe specification protocol and feature set
  • Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
  • Effectively utilize the following features of the gigabit transceivers: 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding, pre-emphasis and receive equalization
  • Use the Transceivers Wizards to instantiate GT primitives in a design
    Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
  • Use the IBERT design to verify transceiver links on real hardware

Course Outline

Day 1Day 2Day 3
  • UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview
  • UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets
  • Transceiver IP Generation Transceiver Wizard
  • LAB: Transceiver Core Generation
  • Use the Transceivers Wizard to create instantiation templates.
  • Transceiver Simulation
  • LAB: Transceiver Simulation
  • Simulate the transceiver IP by using the IP example design.
  • PCS Layer General Functionality
  • PCS Layer Encoding
  • LAB: 64B/66B Encoding
  • Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results
  • Transceiver Implementation
  • LAB: Transceiver Implementation
  • Implement the transceiver IP by using the IP example design
  • LAB: IBERT Design
  • Verify transceiver links on real hardware
  • Transceiver Test and Debugging
  • LAB: Transceiver Debugging
  • Debug transceiver links
  • PCIe Course Introduction
  • Lab: Packet Coding - This lab helps you recall basic PCI Express transaction layer packet formats
  • Xilinx PCI Express Solutions
  • Connecting Logic to the Core AXI Interface
  • PCIe Core Customization
  • LAB: Constructing the PCIe Core - This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
  • Packet Formatting Details
  • Simulating a PCIe System Design
  • LAB: Simulating the PCIe Core - This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.
  • Endpoint Application Considerations
  • PCI Express in Embedded Systems
  • LAB: Using the PCI Express Core in IP Integrator - This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.
  • Application Focus: DMA
  • Design Implementation and PCIe Configuration
  • LAB: Implementing the PCIe Design - This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.
  • Root Port Applications
  • Debugging and Compliance
  • LAB: Debugging the PCIe Design - This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.
  • Interrupts and Error Management
  • Course Summary

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Experience with PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Experience with Xilinx implementation tools
  • Understanding of Xilinx timing constraints
  • Knowledge and experience of Xilinx timing closure
  • Experience with a simulation tool, preferably the Vivado simulator
  • Moderate digital design experience
  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

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Updated 9-02-2021