Designing with SystemVerilog
Designing with SystemVerilog
BLT offers a combined course: Designing and Verification with SystemVerilog.
COURSE CODE: LANG-SVDES
This course provides a thorough introduction to SystemVerilog constructs for design.
This focus is on:
- Writing RTL code using the new constructs available in SystemVerilog
- Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
- Targeting and optimizing AMD FPGAs and adaptive SoC devices using SystemVerilog
In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.
| 2-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $600/day | $1200 | 12 |
| In-Person Public Registration - $600/day | $1200 | 12 |
| Private Training | Learn More | Learn More |
| Coaching | Learn More | Learn More |
| Printed Course Book (A PDF book is included in the course fee) | $200 | 2 |
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Who should attend:
Hardware designers and logic designers.
Software Tools
- Vivado Design Suite
Hardware
- Architecture: N/A*
- Demo board: Zynq™ UltraScale+™ MPSoC ZCU104 board*
* This course does not focus on any particular architecture.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Describe the features and benefits of using SystemVerilog for designing RTL
- Identify the new data types supported in SystemVerilog
- Use an enumerated data type for coding a finite state machine (FSM)
- Explain how to use structures, unions, and arrays
- Describe the new procedural blocks and analyze the affected synthesis results
- Define the enhancements and ability to reuse tasks, functions, and packages
- Identify how to simplify module definitions and instantiations using interfaces
- Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
- Target and optimize AMD FPGAs and adaptive SoCs by using SystemVerilog
- Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
- Download a complete SystemVerilog design to an evaluation board
Course Outline
| Day 1 | Day 2 |
|---|---|
| Introduction to SystemVerilog Provides an introduction to the SystemVerilog language. {Lecture} Data Types Describes the data types supported by SystemVerilog. {Lecture, Demo, Lab} User-Defined and Enumerated Data Types Reviews the user-defined and enumerated data types supported by SystemVerilog. {Lecture} Type Casting Explains type casting in SystemVerilog. {Lecture} Arrays and Strings Covers the use of arrays in SystemVerilog. {Lecture} SystemVerilog Building Blocks Describes the design and verification building blocks in SystemVerilog. {Lecture} Structures Illustrates the use of structures in SystemVerilog. {Lecture, Lab} Unions Reviews the use of unions in SystemVerilog. {Lecture, Lab} Additional Operators in SystemVerilog Describes the operators supported by SystemVerilog beyond those found in Verilog. {Lecture} | Procedural Statements Highlights the different procedural blocks provided by SystemVerilog. {Lecture, Lab} Control Flow Statements Investigates the different control statements provided by SystemVerilog. {Lecture} Functions Explains the SystemVerilog enhancements to functions. {Lecture} Tasks Describes the task SystemVerilog construct. {Lecture} Packages Describes the package SystemVerilog construct. {Lecture, Lab} Interfaces Describes the concept of interfaces in SystemVerilog. {Lecture} Targeting AMD FPGAs and Adaptive SoCs Focuses on AMD-specific implementation and chip-level optimization. {Lecture, Lab} |
Please note: The instructor may change the content order to provide a better learning experience.