Designing with SystemVerilog

BLT offers a combined course: Designing and Verification with SystemVerilog.

This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$5986
In-Person Registration - $399/day$7988
Printed Course Book (mailed to you)$1001
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Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

2 Days

We update our schedule regularly. Stay informed.

Who should attend:

FPGA designers and logic designers.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the features and benefits of using SystemVerilog for RTL design
  • Identify the new data types supported in SystemVerilog
  • Use an enumerated data type for coding a finite state machine (FSM)
  • Explain how to use structures, unions, and arrays
  • Describe the new procedural blocks and analyze the affected synthesis results
  • Define the enhancements and ability to reuse tasks, functions, and packages
  • Identify how to simplify module definitions and instantiations using interfaces
  • Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
  • Target and optimize Xilinx FPGAs by using SystemVerilog
  • Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
  • Download a complete SystemVerilog design to an evaluation board

Course Outline

Day 1Day 2
  • Introduction to SystemVerilog
  • Data Types
  • Demo: SystemVerilog Integer Data Types
  • LAB: SystemVerilog Data Types
    Use enumerated data types to build a finite state machine and perform synthesis to analyze the results.
  • Structures, Unions, and Arrays
  • LAB: Structures and Unions
    Learn about packed and unpacked structures and unions and how to access their members.
  • Additional Operators in System Verilog
  • Procedural Statements and Flow Control
  • LAB: always_ff and always_comb Procedural Blocks
    Learn to use the new procedural blocks always_comb, always_ff, and always_latch to produce the intended synthesized results.
  • Functions, Tasks, and Packages
  • LAB: Functions, Tasks, and Packages
    Create a new package and import that package into the module.
  • Interfaces
  • Targeting Xilinx FPGAs
  • LAB: Interfaces and Design Download
    Use an interface to simplify the module inputs and outputs. Download and verify the design in-circuit.

Please note: The instructor may change the content order to provide a better learning experience.

Updated 4-10-22
©2022 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.