Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users

This course is available as private training only.

COURSE CODE: FPGA-VAXDC4ISE

This course will update experienced ISE software users on how to utilize the AMD Xilinx Vivado Design Suite.

The emphasis is on:

  • Reviewing the underlying database and static timing analysis (STA) mechanisms
  • Utilizing Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports
  • Applying appropriate timing constraints for SDR, DDR, sourcesynchronous, and system-synchronous interfaces
  • Creating path-specific, false path, and min/max timing constraints as well as learning about timing constraint priority in the Vivado timing engine
  • Utilizing a project-based scripting flow
  • Employing FPGA design best practices and the UltraFast Design Methodology to improve design speed and reliability

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$120012
In-Person Public Registration - $600/day$120012
Printed Course Book (A PDF book is included in the course fee)$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

2 Days

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

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Who should attend:

Existing Xilinx ISE Design Suite FPGA designers.

Software Tools

  • Vivado Design or System Edition 2018.1

Hardware

  • Architecture: UltraScale and 7 series FPGAs*
  • Demo board: None*

* This course focuses on the UltraScale and 7 series architectures.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Create appropriate clock and input, output delay constraints and describe timing reports that involve input and output paths
  • Analyze different timing reports
  • Define a properly constrained design
  • Describe setup and hold checks and describe the components of a timing report
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Describe all of the options available with the report_timing and report_timing_summary commands
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Describe the timing constraints required to constrain systemsynchronous and source-synchronous interfaces

Course Outline

Day 1Day 2
  • Introduction to Clock Constraints {Lecture, Lab, Demo}
  • Generated Clocks {Lecture, Demo}
  • Report Clock Networks {Lecture, Demo}
  • Clock Group Constraints {Lecture, Demo}
  • I/O Constraints and Virtual Clocks {Lecture, Lab}
  • Timing Constraints Wizard {Lecture, Lab}
  • Introduction to Vivado Reports {Lecture, Demo}
  • Setup and Hold Timing Analysis {Lecture}
  • Timing Summary Report {Lecture, Demo}
  • Report Clock Interaction {Lecture, Demo}
  • Introduction to Timing Exceptions {Lecture, Lab, Demo}
  • Timing Constraints Priority {Lecture}
  • Synchronization Circuits {Lecture, Lab, Case Study}
  • Report Datasheet {Lecture, Demo}
  • UltraFast Design Methodology: Implementation {Lecture}
  • Baselining {Lecture, Lab, Demo}
  • Pipelining {Lecture, Lab}
  • I/O Timing Scenarios {Lecture}
  • System-Synchronous I/O Timing {Lecture, Demo}
  • Source-Synchronous I/O Timing {Lecture, Lab}
  • Introduction to Floorplanning {Lecture}
  • Congestion {Lecture}
  • Physical Optimization {Lecture, Lab}
  • UltraFast Design Methodology: Design Closure {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Completion of the Vivado Design Suite for ISE Project Navigator Users course is strongly recommended.
  • Working HDL knowledge (VHDL or Verilog)
  • Digital Design Experience

RELATED COURSES:

Updated 12-18-2023
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