Vivado Design Suite Advanced XDC and Static Timing Analysis
Vivado™ Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users
This course will update experienced ISE software users to utilize the Vivado™ Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado™ timing engine. Finally, you will learn about the scripting environment of the Vivado™ Design Suite and how to use the project-based scripting flow.
You will also learn the FPGA design best practices and skills to be successful using the Vivado™ Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado™ software. This course encapsulates this information with an UltraFast® design methodology case study. The UltraFast® design methodology checklist is also introduced.
After completing this comprehensive training, you will know how to:
- Access primary objects from the design database and filter lists of objects using properties
- Describe setup and hold checks and describe the components of a timing report
- Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
- Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
- Describe all of the options available with the report_timing and report_timing_summary commands
- Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
- Analyze a timing report to identify how to center the clock in the data eye
- Create scripts for the project-based and non-project batch design flows
- Describe the UltraFast® design methodology checklist
- Identify key areas to optimize your design to meet your design goals and performance objectives
- Define a properly constrained design
- Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
- Build resets into your system for optimum reliability and design speed
- Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
- Identify timing closure techniques using the Vivado™ Design Suite
- Describe how the UltraFast® design methodology techniques work effectively through case study/lab experience
- UltraFast® Design Methodology: Design Closure
Introduces the UltraFast® design methodology guidelines on design closure.
- UltraFast® Design Methodology: Advanced Techniques
Introduces the methodology guidelines for advanced techniques.
- Timing Constraints Wizard
Use the Timing Constraints Wizard to apply missing timing constraints in a design.
- Timing Constraints Editor
Introduces the timing constraints editor tool to create timing constraints.
- Introduction to Vivado™ Reports
Generate and use Vivado™ timing reports to analyze failed timing paths.
- Introduction to Clock Constraints
Apply clock constraints and perform timing analysis.
- Report Clock Interaction
Use the clock interaction report to identify interactions between clock domains.
- Report Clock Networks
Use report clock networks to view the primary and generated clocks in a design.
- I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis.
- Timing Summary Report
Use the post-implementation timing summary report to sign-off criteria for timing closure.
- Setup and Hold Timing Analysis
Understand setup and hold timing analysis.
- Generated Clocks
Use the report clock networks report to determine if there are any generated clocks in a design.
- Clock Group Constraints
Apply clock group constraints for asynchronous clock domains.
- Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing.
- Synchronization Circuits
Use synchronization circuits for clock domain crossings.
- Report Datasheet
Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
Use Xilinx-recommended baselining procedures to progressively meet timing closure.
Use pipelining to improve design performance.
- I/O Timing Scenarios
Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
- Source-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
- System-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
- Timing Constraints Priority
Identify the priority of timing constraints.
- Case Analysis
Understand how to analyze timing when using multiplexed clocks in a design.
- Introduction to Floorplanning
Introduction to floorplanning and how to use Pblocks while floorplanning.
- Physical Optimization
Use physical optimization techniques for timing closure.
No Scheduled Sessions – Contact Us to ask about setting one up!
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Who should attend:
Existing Xilinx ISE Design Suite FPGA designers
- Experience with the Vivado™ Design Suite
- Working HDL knowledge (VHDL or Verilog)
- Digital design experience