UltraFast Design Methodology

Course Code: FPGA-VDM

BLT helped create the UltraFast Design Methodology for Xilinx (now AMD.) Learn more about the history of the methodology here.

This is an intermediate course. If you are new to AMD FPGAs, start here.

This course describes the FPGA design best practices and skills to be successful using the Vivado Design Suite. Learn how to improve design speed and reliability by using this methodology and the Vivado Design Suite.

The focus is on: 

  • Optimizing system reset design and synchronization circuits
  • Employing best practice HDL coding techniques
  • Applying appropriate timing closure techniques
  • Reviewing an UltraFast Design Methodology case study

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

Live Online Training (9am-5pm ET)
Training Duration:

3 Days

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

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Who should attend:

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Software Tools

  • Vivado Design Suite

Hardware

  • Architecture: UltraScale™ FPGAs*
  • Demo board: None*

* This course focuses on the UltraScale architecture.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the UltraFast design methodology checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

Course Outline

Day 1Day 2Day 3
UltraFast Design Methodology – Planning
  • UltraFast Design Methodology: Introduction
    Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist. {Lecture, Demo}
  • UltraFast Design Methodology: Board and Device Planning
    Introduces the methodology guidelines on board and device planning. {Lecture}
  • Vivado Design Suite I/O Pin Planning
    Describes the I/O Pin Planning layout for performing pin assignments in a design. {Lecture, Lab}
  • Power Estimation Using XPE
    Illustrates estimating the amount of resources and default activity rates for a design and evaluating the estimated power calculated by XPE. {Lecture, Lab}

UltraFast Design Methodology – Design Creation
  • UltraFast Design Methodology: Design Creation
    Introduces the UltraFast methodology guidelines on design creation. {Lecture}
  • RTL Development
    Covers RTL and the RTL design flow, recommended coding guidelines, using control signals, and recommendations on resets. {Lecture}
  • Resets
    Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
  • Pipelining
    Demonstrates the use of pipelining to improve design performance. {Lecture, Lab}
  • Synchronous Design Techniques
    Introduces the synchronous design techniques used in an FPGA design. {Lecture}
Vivado IP Flow
  • Designing with the IP Integrator
    Demonstrates how to use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Lab}
  • Creating and Packaging Custom IP
    Covers creating your own IP and package and including it in the Vivado IP catalog. {Lecture}

Version Control Systems
  • Revision Control Systems in the Vivado Design Suite
    Reviews using version control systems with Vivado IDE design flows. {Lecture}

UltraFast Design Methodology – Implementation
  • UltraFast Design Methodology: Implementation
    Introduces the methodology guidelines on implementation. {Lecture}
  • Incremental Compile Flow
    Discusses the incremental compile flow last-minute RTL changes are made. {Lecture}

UltraFast Design Methodology – Design Analysis
  • UltraFast Design Methodology: Timing Closure
    Introduces the UltraFast methodology guidelines on timing closure. {Lecture}
  • Introduction to Vivado Reports
    Demonstrates generating and using Vivado timing reports to analyze failed timing paths. {Lecture, Demo}
  • Baselining
    Illustrates how to apply recommended baselining procedures to progressively meet timing closure. {Lecture, Lab}
  • Clock Domain Crossing and Synchronization Circuits
    Outlines using synchronization circuits for clock domain crossings. {Lecture}
  • QoR Reports Overview
    Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture, Lab}
  • Timing Closure Using Physical Optimization Techniques
    Shows how to use physical optimization techniques for timing closure. {Lecture, Lab}
  • Power Management Techniques
    Identifies the techniques used for low power design. {Lecture}
Floorplanning
  • Introduction to Floorplanning
    Provides an introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
  • Congestion
    Describes congestion and addresses congestion issues. {Lecture}
Debugging
  • Vivado Design Suite Debug Methodology
    Covers debug core recommendations and employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic HDL knowledge (VHDL or Verilog)
  • Digital design knowledge and experience

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Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.