UltraFast® Design Methodology

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

Please contact the BLT Training Team to schedule a private class.

This course describes the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast® design methodology case study. The UltraFast® design methodology checklist is also introduced.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the UltraFast® Design Methodology Checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the UltraFast® design methodology techniques work effectively through case studies and lab experience

Course Outline

Day 1

  • UltraFast® Design Methodology: Planning
    Introduces the methodology guidelines on planning and the UltraFast® Design Methodology checklist.
  • UltraFast® Design Methodology: Design Creation and Analysis
    Overview of the methodology guidelines on design creation and analysis.
  • HDL Coding Techniques
    Covers basic digital coding guidelines used in an FPGA design.
  • Resets
    Investigates the impact of using asynchronous resets in a design.
  • Register Duplication
    Use register duplication to reduce high fanout nets in a design.
  • Synchronous Design Techniques
    Introduces synchronous design techniques used in an FPGA design.
  • Vivado Design Suite I/O Pin Planning
    Use the I/O Pin Planning layout to perform pin assignments in a design.
  • Vivado Design Rule Checks
    Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
  • Creating and Packaging Custom IP
    Create your own IP and package and include it in the Vivado IP catalog.

Day 2

  • UltraFast® Design Methodology: Design Closure
    Introduces the UltraFast® methodology guidelines on design closure.
  • UltraFast® Design Methodology: Advanced Techniques
    Introduces the methodology guidelines for advanced techniques.
  • Baselining
    Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  • Pipelining
    Use pipelining to improve design performance.
  • Inference
    Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
  • Revision Control Systems in the Vivado Design Suite
    Use version control systems with Vivado design flows.
  • Synchronization Circuits
    Use synchronization circuits for clock domain crossings.
  • Introduction to Floorplanning
    Introduction to floorplanning and how to use Pblocks while floorplanning.
  • Physical Optimization
    Use physical optimization techniques for timing closure.
  • Power Management Techniques
    Identify techniques used for low power design.
  • Vivado Design Suite Debug Methodology
    Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer.

Training Duration:

2 Days

Who should attend:

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.


  • Some knowledge of FPGA design techniques is helpful
  • Experience with the Vivado Design Suite or attendance of one of our existing Vivado Design Suite training courses is required
  • Intermediate knowledge of Verilog or VHDL

Version: 2021-03-17_0932

Updated 7-10-22
©2022 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.