Designing with the Versal Adaptive SoC: Architecture and Methodology

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Designing with the Versal Adaptive SoC (formerly ACAP): Architecture and Methodology

Course Code: ACAP-ARCH

This course helps you to learn about AMD Xilinx Versal Adaptive SoC (formerly called ACAP) architecture and design methodology.

The emphasis of this course is on reviewing the architecture of the Versal Adaptive SoC, describing the different engines available in the Versal architecture and what resources they contain, utilizing the hardened blocks available in the Versal architecture, using the design tools and methodology provided by Xilinx to create complex systems, describing the network on chip (NoC) and AI Engine concepts and their architectures, and performing system-level simulation and debugging.

Click here for more information about the AMD Versal Adaptive SoC.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

TRAINING DURATION:

3 Days

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Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal Adaptive SoC device.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the Versal Adaptive SoC architecture at a high level
  • Describe the various engines in the Versal Adaptive SoC device
  • Use the various blocks from the Versal architecture to create complex systems
  • Perform system-level simulation and debugging
  • Identify and apply different design methodologies

Course Outline

Day 1Day 2Day 3
  • Introduction {Lecture}
  • Architecture Overview {Lecture}
  • Design Tool Flow {Lecture, Lab}
  • Adaptable Engines (PL) {Lecture}
  • Processing System {Lecture}
  • PMC and Boot and Configuration {Lecture, Lab}
  • SelectIO Resources {Lecture}
  • Clocking Architecture {Lecture, Lab}
  • System Interrupts {Lecture}
  • Timers, Counters, and RTC {Lecture}
  • Software Build Flow {Lecture, Lab}
  • Software Stack {Lecture}
  • DSP Engine {Lecture}
  • AI Engine {Lecture}
  • NoC Introduction and Concepts {Lecture, Lab}
  • Device Memory {Lecture}
  • Programming Interfaces {Lecture}
  • Application Partitioning {Lecture}
  • PCI Express & CCIX {Lecture, Lab}
  • Serial Transceivers {Lecture}
  • Power and Thermal Solutions {Lecture}
  • Debugging {Lecture, Lab}
  • Security Features {Lecture}
  • System Simulation {Lecture, Lab}
  • System Design Methodology {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Comfort with the C/C++ programming language
  • Vitis IDE software development flow
  • Hardware development flow with the Vivado Design Suite
  • Basic knowledge of UltraScale/UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs

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Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

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