Designing with the Versal ACAP: Architecture and Methodology
Designing with the Versal ACAP: Architecture and Methodology
This course helps you to learn about AMD Xilinx Versal® ACAP architecture and design methodology.
The emphasis of this course is on reviewing the architecture of the Versal ACAP, describing the different engines available in the Versal architecture and what resources they contain, utilizing the hardened blocks available in the Versal architecture, using the design tools and methodology provided by Xilinx to create complex systems, describing the network on chip (NoC) and AI Engine concepts and their architectures, and performing system-level simulation and debugging.
Click here for more information about the Xilinx Versal ACAP.
3-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $299/day | $897 | 9 |
In-Person Registration - $399/day | $1197 | 12 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
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Who should attend:
Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the Versal ACAP architecture at a high level
- Describe the various engines in the Versal ACAP device
- Use the various blocks from the Versal architecture to create complex systems
- Perform system-level simulation and debugging
- Identify and apply different design methodologies
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Comfort with the C/C++ programming language
- Vitis IDE software development flow
- Hardware development flow with the Vivado Design Suite
- Basic knowledge of UltraScale/UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs