Designing with Versal AI Engine: Architecture and Design Flow – 1

Course Code: AIE-ARCH

This course describes the AMD Versal AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features.

The emphasis of this course is on:

  • Illustrating the AI Engine architecture
  • Designing single AI Engine kernels using the Vitis unified software platform
  • Designing multiple AI kernels using data flow graphs with the Vitis IDE
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
  • Analyzing and debugging kernel performance

Click here for more information about the AMD Versal Adaptive SoC. (formerly ACAP)

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

Live Online Training (9am-5pm ET)
View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

Be the first to know. Sign up for our newsletter.

Who should attend:

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using our devices.

Software Tools

  • Vitis unified software platform


  • Architecture: Versal adaptive SoCs

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the Versal adaptive SoC architecture at a high level
  • Describe the various engines in the Versal device and the motivation behind the AI Engine
  • Describe the architecture of the AI Engine
  • Describe the memory access structure for the AI Engine
  • Describe the full application acceleration flow with the Vitis tool
  • Enumerate the toolchain for Versal AI Engine programming
  • Explain what AI Engine APIs are
  • Program a single AI Engine kernel using the Vitis IDE tool
  • Program multiple AI Engine kernels using Adaptive Data Flow (ADF) graphs

Course Outline

Day 1Day 2Day 3

Versal Adaptive SoC Architecture

  • Overview of the AMD Versal Adaptive SoC Architecture
    Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal device, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines. Also describes how the AI Engine in the Versal device meets many dynamic market needs. {Lecture}

Versal AI Engine Architecture

  • Versal AI Engine Architecture
    Introduces the architecture of the AI Engine and its components. {Lecture}
  • AI Engine Interfaces
    Describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces. {Lecture}
  • Versal AI Engine Memory and Data Movement
    Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays. {Lecture}

Vitis Tool Flow

  • Versal AI Engine Tool Flow
    Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Labs}

    Design Analysis

    • Versal Adaptive SoC: Application Partitioning 1
      Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal device. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal adaptive SoC. {Lecture}

    The Programming Model

    • Scalar and Vector Data Types
      Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. {Lecture}
    • AI Engine APIs
      Describes what AI Engine APIs are, the three types of vector manipulation operations using AI Engine APIs (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions. {Lecture}

    Design Analysis

    • Vitis Analyzer
      Describes the different reports generated by the tool and how to view the reports that help to optimize and debug AI Engine kernels using the Vitis analyzer tool. {Lecture}

      The Programming Model

      • Windows, Buffers, and Streaming Data APIs
        Describes window, i/o buffers and streaming data APIs and reviews the various buffer operations for kernels. {Lecture}
      • The Programming Model: Single Kernel
        Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the Vitis IDE tool. {Lecture, Lab}
      • The Programming Model: Single Kernel Using Vector Data Types
        Illustrates Versal AI Engine kernel programming in detail, reviewing the scalar kernel code and comparing with vector kernel code that utilizes AI Engine APIs and vector data types. {Lab}
      • The Programming Model: Introduction to the Adaptive Data Flow (ADF) Graph
        Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports. {Lecture}
      • The Programming Model: Multiple Kernels Using Graphs
        Describes the ADF graph in detail and demonstrates the steps to create a graph and set the runtime ratio and graph control APIs from the main application program. {Lecture, Lab}

      Please note: The instructor may change the content order to provide a better learning experience.

      Updated 12-18-2023
      ©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.