Designing with Versal AI Engine 1: Architecture and Design Flow

This course, Versal^® AI Engine 1, describes the Xilinx® Versal AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to utilize the AI Engine library for faster development.

The emphasis of this course is on illustrating the AI Engine architecture, designing single AI Engine kernels, designing multiple AI kernels using data flow graphs with the Vitis^™ IDE, reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL), and analyzing and debugging kernel performance.

Click here for more information about the Xilinx Versal ACAP.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

Live Online Training (9am-5pm ET)

July 26-27, 2023 | Register Today

November 8-9, 2023 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

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Who should attend:

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the Versal ACAP architecture at a high level
Describe the various engines in the Versal ACAP device and the motivation behind the AI Engine
Also describe the architecture of the AI Engine
Describe the memory access structure for the AI Engine
Describe the full application acceleration flow with the Vitis tool
Enumerate the toolchain for Versal AI Engine programming
Explain what intrinsic functions are
Program a single AI Engine Kernel
Program multiple AI Engine kernels using static data flow (SDF) graphs

Course Outline

Day 1	Day 2
Overview of Versal ACAP Architecture {Lecture} Introduction to the Versal AI Engine Architecture {Lecture} Versal AI Engine Memory and Data Movement {Lecture} Versal AI Engine Tool Flow {Lecture, Lab} Application Partitioning on Versal ACAPs {Lecture} Data Types: Scalar and Vector Data Types {Lecture} Intrinsic Functions {Lecture}	Window and Streaming Data APIs {Lecture} The Programming Model: Single Kernel {Lecture, Lab} The Programming Model: Introduction to the Data Flow Graph {Lecture} The Programming Model: Multiple Kernels Using Graphs {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Must have taken the Network on Chip or Versal Architecture or be familiar with NoC content
Comfort with the C/C++ programming language
Software development flow
Vitis software for application acceleration development flow

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Updated 3-22-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.