Zynq UltraScale+ MPSoC for the Software Developer

BLT offers a similiar course under a different name: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

This two-day course is structured to provide software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq^® UltraScale+^™ MPSoC family.

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2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

See available class dates for Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

Training Duration:

2 Days

The BLT Adaptive Computing Summit

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April 25: Columbia, MD • May 2: Melbourne, FL • May 4: Orlando, FL • May 17: Huntsville, AL

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Who should attend:

Software developers interested in understanding the OS and other capabilities of the Zynq UltraScale+ MPSoC device.

Skills Gained

After completing this comprehensive training, you will know how to:

Distinguish between asymmetric multi-processing (AMP) and symmetric multi-processing (SMP) environments
Identify situations when the ARM^™ TrustZone technology and/or a hypervisor should be used
Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)
Define the boot sequences appropriate to the needs of the system
Define the underlying implementation of the application processing unit (APU) and real-time processing unit (RPU) to make best use of their capabilities

Course Outline

Day 1	Day 2
Zynq UltraScale+ MPSoC Application Processing Unit Introduction to the members of the APU, specifically the Cortex^®-A53 processor and how the cluster is configured and managed. Zynq UltraScale+ MPSoC Real-Time Processing Unit Introduction to the various elements within the RPU and different modes of configuration. ARM TrustZone Technology Illustrates the use of the ARM TrustZone technology. QEMU Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available. Zynq UltraScale+ MPSoC HW-SW Virtualization Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used. Multiprocessor Software Architecture Introduces several potential architectures and illustrate the strengths of each. Xen Hypervisor (pairs with OpenAMP, but not SMP) Description of generic hypervisors and discussion of some of the details of implementing a hypervisor using Xen. OpenAMP (pairs with the Xen Hypervisor, but not SMP) Introduction to the concept of OpenAMP. Linux Discussion and examples showing how to configure Linux to manage multiple processors.	Yocto Compares and contrasts the kernel building methods between a "pure" Yocto build and the PetaLinux build (which uses Yocto "under-the-hood") Open Source Library Introduction to open-source Linux and the effort and risk-reducing PetaLinux tools. FreeRTOS Overview of FreeRTOS with examples of how it can be used. Zynq UltraScale+ MPSoC Software Stack Introduction to what a software stack is and a number of stacks used with the Zynq UltraScale+ MPSoC. Zynq UltraScale+ MPSoC PMU Investigation into the the tools and techniques for debugging a Zynq UltraScale+ MPSoC device. Zynq UltraScale+ MPSoC Power Management Overview of the PMU and the power-saving features of the device. Zynq UltraScale+ MPSoC Booting How to implement the embedded system, including the boot process and boot image creation.

Day 1

Day 2

Zynq UltraScale+ MPSoC Application Processing Unit
Introduction to the members of the APU, specifically the Cortex^®-A53 processor and how the cluster is configured and managed.
Zynq UltraScale+ MPSoC Real-Time Processing Unit
Introduction to the various elements within the RPU and different modes of configuration.
ARM TrustZone Technology
Illustrates the use of the ARM TrustZone technology.
QEMU
Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
Zynq UltraScale+ MPSoC HW-SW Virtualization
Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
Multiprocessor Software Architecture
Introduces several potential architectures and illustrate the strengths of each.
Xen Hypervisor (pairs with OpenAMP, but not SMP)
Description of generic hypervisors and discussion of some of the details of implementing a hypervisor using Xen.
OpenAMP (pairs with the Xen Hypervisor, but not SMP)
Introduction to the concept of OpenAMP.
Linux
Discussion and examples showing how to configure Linux to manage multiple processors.

Yocto
Compares and contrasts the kernel building methods between a "pure" Yocto build and the PetaLinux build (which uses Yocto "under-the-hood")
Open Source Library
Introduction to open-source Linux and the effort and risk-reducing PetaLinux tools.
FreeRTOS
Overview of FreeRTOS with examples of how it can be used.
Zynq UltraScale+ MPSoC Software Stack
Introduction to what a software stack is and a number of stacks used with the Zynq UltraScale+ MPSoC.
Zynq UltraScale+ MPSoC PMU
Investigation into the the tools and techniques for debugging a Zynq UltraScale+ MPSoC device.
Zynq UltraScale+ MPSoC Power Management
Overview of the PMU and the power-saving features of the device.
Zynq UltraScale+ MPSoC Booting
How to implement the embedded system, including the boot process and boot image creation.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

General understanding of embedded and real-time operating systems
Familiarity with issues related to implementing a complex embedded system

RELATED COURSES:

Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

Updated 3-22-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.