Designing with the UltraScale and UltraScale+ Architectures

COURSE CODE: FPGA-US

This course introduces the AMD UltraScale and UltraScale+ architectures to both new and experienced designers.

The emphasis is on:

  • Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
  • Describing improvements to the dedicated transceivers and Transceiver Wizard
  • Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
  • Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado Design Suite

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

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Who should attend:

Anyone who would like to build a design for the UltraScale or UltraScale+ device family.

Software Tools

  • Vivado Design Suite

Hardware

  • Architecture: UltraScale and UltraScale+ FPGAs*
  • Demo board: None*

* This course focuses on the UltraScale and UltraScale+ architectures.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary AMD UltraScale architecture resources
  • Describe the new CLB capabilities and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO, and DSP resources available
  • Describe the new type of memory structures available in UltraScale+ devices, such as UltraRAM and the high bandwidth memory (HBM) available in Virtex UltraScale+ devices
  • Properly design for the I/O and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included
  • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1Day 2Day 3
Introduction to the UltraScale Architecture
Review the UltraScale architecture, which includes enhanced CLB resources, DSP resources, etc. {Lecture}

UltraScale Architecture CLB Resources
Examine the CLB resources, such as the LUT and the dedicated carry chain, in the UltraScale architecture. {Lecture, Lab}

HDL Coding Techniques Covers basic digital coding guidelines used in an FPGA design. {Lecture, Lab}

UltraScale Architecture Clocking Resources Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks. {Lectures, Lab}

FPGA Design Migration
Migrate an existing 7 series design to the UltraScale architecture. {Lecture, Lab}

Clocking Migration Migrate a 7 series design to the UltraScale architecture with a focus on clocking resources. {Lab}

UltraScale Architecture Block RAM Memory Resources Review the block RAM resources in the UltraScale architecture. {Lecture}

UltraScale Architecture FIFO Memory Resources
Review the FIFO resources in the UltraScale architecture. {Lecture}
UltraRAM Memory
Use UltraRAM for a design requiring a larger memory size than block RAM. {Lecture, Lab}

High Bandwidth Memory
Use high bandwidth memory (HBM) for applications requiring high bandwidth. {Lecture, Demo}

UltraScale Architecture DSP Resources
Review the DSP resources in the UltraScale architecture. {Lecture, Lab}

Design Migration Software Recommendations
List the Xilinx software recommendations for design migrations from 7 series to the UltraScale architecture. {Lecture}

DDR3 MIG Design Migration Migrate a 7 series MIG design to the UltraScale architecture. {Lab}

DDR4 Design Creation Using MIG
Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility. {Lab}

UltraScale Architecture I/O Resources
Overview Review the I/O resources in the UltraScale architecture. {Lecture}

UltraScale Architecture I/O Resources: Component Mode
Implement a high-performance, source-synchronous interface using I/O resources in Component mode for the UltraScale architecture. {Lecture, Lab}
UltraScale Architecture I/O Resources: Native Mode Implement a high-performance, source-synchronous interface using I/O resources in Native mode for the UltraScale architecture. {Lecture, Lab}

Design Migration Methodology
Review the migration methodology recommended by Xilinx for design migrations. {Lecture}

10G PCS/PMA and MAC Design Migration
Migrate a successfully implemented 7 series design containing the 10G Ethernet MAC and 10G PCS/PMA IP to an UltraScale FPGA. {Lab}

UltraScale Architecture Transceivers
Review the enhanced features of the transceivers in the UltraScale architecture. {Lecture}

UltraScale FPGAs Transceivers Wizard
Use the Transceivers Wizard to build a design that uses a single serial transceiver and observe the created file structures. {Lecture, Demo, Lab}

Introduction to the UltraScale+ Families
Identify the enhancements made to the UltraScale architecture in the UltraScale+ architecture families. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

RELATED COURSES:

Updated 12-18-2023
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