Designing with the Ultrascale™ and Ultrascale+™ Architectures
Designing with the Ultrascale™ and Ultrascale+™ Architectures
This course introduces new and experienced designers to the most sophisticated aspects of the Ultrascale™ and Ultrascale+™ architectures. Targeted towards designers who have used the Vivado™ Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families.
Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.
In addition, you will learn how to best migrate your design and IP to the Ultrascale™ architecture and the best way to use the Vivado™ Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
Skills Gained
After completing this comprehensive training, you will know how to:
- Take advantage of the primary Ultrascale™ architecture resources
- Describe the new CLB capabilities and the impact that they make on your HDL coding style
- Define the block RAM, FIFO, and DSP resources available
- Describe the UltraRAM features
- Properly design for the I/O and SERDES resources
- Identify the MMCM, PLL, and clock routing resources included
- Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
- Describe the additional features of the dedicated transceivers
- Effectively migrate your IP and design to the Ultrascale™ architecture as quickly as possible
Course Outline
Day 1
- Introduction to the Ultrascale™ Architecture
Review the Ultrascale™ architecture, which includes enhanced CLB resources, DSP resources, etc. - Ultrascale™ Architecture CLB Resources
Examine the CLB resources, such as the LUT and the dedicated carry chain in the Ultrascale™ architecture. - HDL Coding Techniques
Analyze a design that has asynchronous resets by generating various reports, such as the Timing Summary report and Utilization report. Convert the asynchronous resets to synchronous resets by removing the reset signal from the sensitivity list. - Ultrascale™ Architecture Clocking Resources
Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks. - FPGA Design Migration
Migrate an existing 7 series design to the Ultrascale™ architecture. - Clocking Migration
Migrate a 7 series design to the Ultrascale™ architecture with a focus on clocking resources. - Ultrascale™ Architecture Block RAM Memory Resources
Review the block RAM resources in the Ultrascale™ architecture. - Ultrascale™ Architecture FIFO Memory Resources
Review the FIFO resources in the Ultrascale™ architecture. - UltraRAM Memory
Use UltraRAM for a design requiring a larger memory size than block RAM. - Ultrascale™ Architecture DSP Resources
Review the DSP Resources in the Ultrascale™ architecture.
Day 2
- Design Migration Software Recommendations
List the Xilinx software recommendations for design migrations from 7 series to the Ultrascale™ architecture. - DDR3 MIG Design Migration
Migrate a 7 series MIG design to the Ultrascale™ architecture. - DDR4 Design Creation Using MIG
Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility. - Ultrascale™ Architecture I/O Resources Overview
Review the I/O resources in the Ultrascale™ architecture. - Ultrascale™ Architecture I/O Resources Component Mode
Implement a high-performance, source-synchronous interface using I/O resources in Component mode for the Ultrascale™ architecture. - Ultrascale™ Architecture I/O Resources Native Mode
Implement a high-performance, source-synchronous interface using I/O resources in Native mode for the Ultrascale™ architecture. - Design Migration Methodology
Review the migration methodology recommended by Xilinx for design migrations. - 10G PCS/PMA and MAC Design Migration
Migrate a successfully implemented 7 series design containing the 10G Ethernet MAC and 10G PCS/PMA IP to an Ultrascale™ FPGA. - Ultrascale™ Architecture Transceivers
Review the enhanced features of the transceivers in the Ultrascale™ architecture. - Ultrascale™ FPGAs Transceivers Wizard
Use the Transceivers Wizard to build a design that uses a single serial transceiver and observe the created file structures. - Introduction to the Ultrascale+™ Families
Identify the enhancements made to the Ultrascale™ architecture in the Ultrascale+™ architecture families.
No Scheduled Sessions - Contact Us to ask about setting one up!
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Training Duration:
2 Days
Who should attend:
Anyone who would like to build a design for the Ultrascale™ or Ultrascale+™ device family
Prerequisites
Designing FPGAs Using the Vivado™ Design Suite 1 course
Intermediate VHDL or Verilog knowledge
Software Tools
Vivado™ Design or System Edition 2017.1
Hardware
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