Assured Synthesis Key (ASK) Assurance Toolkit
BLT’s innovative Assured Synthesis Key (ASK) technology provides data provenance assurance, data and workflow content verification, and resistance to evasion-style attacks for FPGA/SoC development. ASK enables EDA projects and workflows to allow for consistent reproduction and to provide a method to detect, report, and revert deviations in data and metadata without disrupting the EDA process consistently and accurately.
Do you know if your FPGA / SoC designs have been inadvertently or maliciously changed?
Available Now for Early Release:
These versions of the ASK tool are available now for early release.
Coming Soon:
These versions of the ASK tool will be available shortly.
ASK-D for Lattice Diamond
ASK-L for Microchip Libero
Fill out our form or email us at [email protected].
About
Originally, BLT developed ASK technology in response to a community requirement for a very specific data integrity challenge. In developing ASK, BLT discovered a lack of “hygiene” or discipline in maintaining data files, processes/workflows, and the resulting work products, even in a classified environment, as well as corresponding threats of data manipulation and even theft. ASK technology provides robust configuration management, content verification and data provenance assurance. At a high-level ASK’s primary capabilities/features include the detection of changes, auditing of EDA tools and projects, the ability to revert changes, and finally integrates and automatically drives EDA tools through their build flows.
Ready to provide assurance for your FPGA / SoC Design process?
Contact us today to get started.