Designing FPGAs Using the Vivado Design Suite 1

This course offers introductory training on the Vivado Design Suite and helps you to understand the FPGA design flow. For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Generate a DRC report to detect and fix design issues early in the flow
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Synthesize and implement the HDL design
  • Apply clock and I/O timing constraints and perform timing analysis
  • Describe the "baselining" process to gain timing closure on a design
  • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
  • Use the Vivado logic analyzer and debug flows to debug a design

Course Outline

Day 1

  • Introduction to FPGA Architecture, 3D IC, SoCOverview of FPGA architecture, SSI technology, and SoC device architecture.
  • UltraFast® Design Methodology: PlanningIntroduces the methodology guidelines covered in this course and the UltraFast® Design Methodology checklist.
  • HDL Coding TechniquesCovers basic digital coding guidelines used in an FPGA design.
  • Introduction to Vivado Design FlowsIntroduces the Vivado design flows: the project flow and non-project batch flow.
  • Vivado Design Suite Project ModeCreate a project, add files to the project, explore the Vivado IDE, and simulate the design.
  • Synthesis and ImplementationCreate timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
  • Basic Design Analysis in the Vivado IDEUse the various design analysis features in the Vivado Design Suite.
  • Vivado Design Rule ChecksRun a DRC report on the elaborated d

Day 2

  • Introduction to Clock ConstraintsApply clock constraints and perform timing analysis.
  • I/O Constraints and Virtual ClocksApply I/O constraints and perform timing analysis.
  • Setup and Hold Timing AnalysisUnderstand setup and hold timing analysis.
  • Report Clock NetworksUse report clock networks to view the primary and generated clocks in a design.
  • Xilinx Power Estimator SpreadsheetEstimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
  • Introduction to FPGA ConfigurationDescribes how FPGAs can be configured.
  • Introduction to the Vivado Logic AnalyzerOverview of the Vivado logic analyzer for debugging a design.
  • Introduction to TriggeringIntroduces the trigger capabilities of the Vivado logic analyzer.
  • Debug CoresUnderstand how the debug hub core is used to connect debug cores in a design.
  • HDL Instantiation Debug Probing FlowCovers the HDL instantiation flow to create and

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,600
Standard Registration
16 Training Credits
Advanced Registration
$1,400
Advanced Registration
14 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$700
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite

Prerequisites

Basic knowledge of the VHDL or Verilog language

Digital design knowledge

Software Tools

Vivado Design or System Edition 2017.1

Hardware

Architecture: Ultrascale and 7 series FPGAs*Demo board (optional): Kintex Ultrascale FPGA KCU105 board or Kintex-7 FPGA KC705 board** This course focuses on the Ultrascale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626