$299/Day - Designing FPGAs Using the Vivado Design Suite 1

Designing FPGAs Using the Vivado Design Suite 1

BLT offers Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO which contains the core modules from this course, plus additional relevant material.

This course offers introductory training on the Xilinx® Vivado® Design Suite and helps you to understand the FPGA design flow.

For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

See available class dates for Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO

Training Duration:

2 Days

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Who should attend:

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite.

Skills Gained

After completing this comprehensive training, you will know how to:

Use the New Project Wizard to create a new Vivado IDE project
Describe the supported design flows of the Vivado IDE
Generate a DRC report to detect and fix design issues early in the flow
Use the Vivado IDE I/O Planning layout to perform pin assignments
Synthesize and implement the HDL design
Apply clock and I/O timing constraints and perform timing analysis
Describe the “baselining” process to gain timing closure on a design
Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
Use the Vivado logic analyzer and debug flows to debug a design

Course Outline

Day 1	Day 2
Introduction to FPGA Architecture, 3D IC, SoC Overview of FPGA architecture, SSI technology, and SoC device architecture. UltraFast™ Design Methodology: Planning Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. HDL Coding Techniques Covers basic digital coding guidelines used in an FPGA design. Introduction to Vivado Design Flows Introduces the Vivado design flows: the project flow and non-project batch flow. Vivado Design Suite Project Mode Create a project, add files to the project, explore the Vivado IDE, and simulate the design. Synthesis and Implementation Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. Basic Design Analysis in the Vivado IDE Use the various design analysis features in the Vivado^™ Design Suite. Vivado Design Rule Checks Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. Vivado Design Suite I/O Pin Planning Use the I/O Pin Planning layout to perform pin assignments in a design. Vivado IP Flow Customize IP, instantiate IP, and verify the hierarchy of your design IP. Timing Constraints Wizard Use the Timing Constraints Wizard to apply missing timing constraints in a design. Timing Constraints Editor Introduces the timing constraints editor tool to create timing constraints. Introduction to Vivado Reports Generate and use Vivad timing reports to analyze failed timing paths.	Introduction to Clock Constraints Apply clock constraints and perform timing analysis. I/O Constraints and Virtual Clocks Apply I/O constraints and perform timing analysis. Setup and Hold Timing Analysis Understand setup and hold timing analysis. Report Clock Networks Use report clock networks to view the primary and generated clocks in a design. Xilinx Power Estimator Spreadsheet Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. Introduction to FPGA Configuration Describes how FPGAs can be configured. Introduction to the Vivado Logic Analyzer Overview of the Vivado logic analyzer for debugging a design. Introduction to Triggering Introduces the trigger capabilities of the Vivado logic analyzer. Debug Cores Understand how the debug hub core is used to connect debug cores in a design. HDL Instantiation Debug Probing Flow Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer. Netlist Insertion Debug Probing Flow Use the Netlist Insertion flow to insert ILA cores into an existing synthesized netlist and debug a common problem. Introduction to the Tcl Environment Introduces Tcl (tool command language). Using Tcl Commands in a Vivado Design Suite Project Flow Explains what Tcl commands are executed in a Vivado Design Suite project flow. Tcl Syntax and Structure Understand the Tcl syntax and structure.

Day 1

Day 2

Introduction to FPGA Architecture, 3D IC, SoC
Overview of FPGA architecture, SSI technology, and SoC device architecture.
UltraFast™ Design Methodology: Planning
Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design.
Introduction to Vivado Design Flows
Introduces the Vivado design flows: the project flow and non-project batch flow.
Vivado Design Suite Project Mode
Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
Basic Design Analysis in the Vivado IDE
Use the various design analysis features in the Vivado^™ Design Suite.
Vivado Design Rule Checks
Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments in a design.
Vivado IP Flow
Customize IP, instantiate IP, and verify the hierarchy of your design IP.
Timing Constraints Wizard
Use the Timing Constraints Wizard to apply missing timing constraints in a design.
Timing Constraints Editor
Introduces the timing constraints editor tool to create timing constraints.
Introduction to Vivado Reports
Generate and use Vivad timing reports to analyze failed timing paths.

Introduction to Clock Constraints
Apply clock constraints and perform timing analysis.
I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis.
Setup and Hold Timing Analysis
Understand setup and hold timing analysis.
Report Clock Networks
Use report clock networks to view the primary and generated clocks in a design.
Xilinx Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
Introduction to FPGA Configuration
Describes how FPGAs can be configured.
Introduction to the Vivado Logic Analyzer
Overview of the Vivado logic analyzer for debugging a design.
Introduction to Triggering
Introduces the trigger capabilities of the Vivado logic analyzer.
Debug Cores
Understand how the debug hub core is used to connect debug cores in a design.
HDL Instantiation Debug Probing Flow
Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
Netlist Insertion Debug Probing Flow
Use the Netlist Insertion flow to insert ILA cores into an existing synthesized netlist and debug a common problem.
Introduction to the Tcl Environment
Introduces Tcl (tool command language).
Using Tcl Commands in a Vivado Design Suite Project Flow
Explains what Tcl commands are executed in a Vivado Design Suite project flow.
Tcl Syntax and Structure
Understand the Tcl syntax and structure.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of the VHDL or Verilog language
Digital design knowledge

RELATED COURSES:

Updated 7-14-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.