Designing FPGAs Using the Vivado Design Suite 1
Designing FPGAs Using the Vivado Design Suite 1
BLT offers Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO and Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging which contain modules from this course.
This course offers introductory training on the Xilinx® Vivado® Design Suite and helps you to understand the FPGA design flow.
For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.
2-Day Instructor-led Course | Price USD | Training Credits |
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Hosted Online - $299/day | $598 | 6 |
In-Person Registration - $399/day | $798 | 8 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
Training Duration:
2 Days
The BLT Adaptive Computing Summit
Emerging Solutions for Outer Space, Undersea, and Everywhere in Between
April 25: Columbia, MD • May 2: Melbourne, FL • May 4: Orlando, FL • May 17: Huntsville, AL
Who should attend:
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite.
Skills Gained
After completing this comprehensive training, you will know how to:
- Use the New Project Wizard to create a new Vivado IDE project
- Describe the supported design flows of the Vivado IDE
- Generate a DRC report to detect and fix design issues early in the flow
- Use the Vivado IDE I/O Planning layout to perform pin assignments
- Synthesize and implement the HDL design
- Apply clock and I/O timing constraints and perform timing analysis
- Describe the “baselining” process to gain timing closure on a design
- Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
- Use the Vivado logic analyzer and debug flows to debug a design
Course Outline
Day 1 | Day 2 |
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge