$299/Day - Essential DSP Implementation Techniques for Xilinx FPGAs

Essential DSP Implementation Techniques for Xilinx FPGAs

This class is now taught as DAY 1 of our Vitis Model Composer: A MATLAB and Simulink-based Product. Please view that class for available dates.

This course provides a foundation for Digital Signal Processing (DSP) implementation techniques for Xilinx® FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.

Learn more about Xilinx DSP implementation.

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$299	3
In-Person Registration - $399/day	$399	4
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

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Who should attend:

Engineers and designers who have an interest in developing products that use digital signal processing.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the advantages of using FPGAs over traditional processors for DSP designs
Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
Explain the algorithms for video and imaging systems and their implementations in FPGAs

Course Outline

Day 1
Back to Basics Architecture FPGA Math LAB: Signed Number Conversion, Quantization and Rounding, Adders, Subtractors, and Accumulation Learn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions. Shift Registers, RAM, and Applications LAB: SRL32E and RAM Estimation and Concatenation Learn how to optimize memory and storage in Xilinx FPGAs. FIR Filter LAB: Filter Implementation, Resource and Performance Estimation Learn how and when to use various implementation strategies for optimal filter implementation. Advanced Filter Techniques LAB: Filter Implementations, Resource and Performance Estimation Advanced filter topologies are studied. Architect multichannel and multirate filters using various methods. Implementation strategies will be discussed and optimal methods used. Fast Fourier Transform LAB: FFT Implementation, Resource and Performance Estimation Select correct parameters for FFT implementations to meet design targets. Resource estimation will be studied and trade-offs with performance examined through implementation examples. Video and Imaging Where Do We Go From Here? Demonstration: System Generator and the CORE Generator™ Tool with a DSP-Targeted Reference Design Targeted Reference Design Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of Xilinx DSP tools and IP. Reinforce the concepts studied in the course material and exercises. Where Can I Learn More?

Day 1

Back to Basics
Architecture
FPGA Math
LAB: Signed Number Conversion, Quantization and Rounding, Adders, Subtractors, and Accumulation
Learn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions.
Shift Registers, RAM, and Applications
LAB: SRL32E and RAM Estimation and Concatenation
Learn how to optimize memory and storage in Xilinx FPGAs.
FIR Filter
LAB: Filter Implementation, Resource and Performance Estimation
Learn how and when to use various implementation strategies for optimal filter implementation.
Advanced Filter Techniques
LAB: Filter Implementations, Resource and Performance Estimation
Advanced filter topologies are studied. Architect multichannel and multirate filters using various methods. Implementation strategies will be discussed and optimal methods used.
Fast Fourier Transform
LAB: FFT Implementation, Resource and Performance Estimation
Select correct parameters for FFT implementations to meet design targets. Resource estimation will be studied and trade-offs with performance examined through implementation examples.
Video and Imaging
Where Do We Go From Here?
Demonstration: System Generator and the CORE Generator™ Tool with a DSP-Targeted Reference Design
Targeted Reference Design Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of Xilinx DSP tools and IP. Reinforce the concepts studied in the course material and exercises.
Where Can I Learn More?

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

A fundamental understanding of digital signal processing theory, including an understanding of the following principles
Sample rates
Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters
Oscillators and mixers
Fast Fourier Transform (FFT) algorithm

RELATED COURSES:

Updated 7-14-2023

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