Essential DSP Implementation Techniques for Xilinx FPGAs

This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the advantages of using FPGAs over traditional processors for DSP designs
  • Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
  • Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
  • Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
  • Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
  • Explain the algorithms for video and imaging systems and their implementations in FPGAs

Course Outline

Day 1

  • Back to Basics
  • Architecture
  • FPGA Math
  • Lab 1: Signed Number Conversion, Quantization and Rounding, Adders, Subtractors, and AccumulationLearn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions.
  • Shift Registers, RAM, and Applications
  • Lab 2: SRL32E and RAM Estimation and ConcatenationLearn how to optimize memory and storage in Xilinx FPGAs.
  • FIR Filter
  • Lab 3: Filter Implementation, Resource and Performance EstimationLearn how and when to use various implementation strategies for optimal filter implementation.

Day 2

  • Advanced Filter Techniques
  • Lab 4: Filter Implementations, Resource and Performance EstimationAdvanced filter topologies are studied. Architect multichannel and multirate filters using various methods. Implementation strategies will be discussed and optimal methods used.
  • Fast Fourier Transform
  • Lab 5: FFT Implementation, Resource and Performance EstimationSelect correct parameters for FFT implementations to meet design targets. Resource estimation will be studied and trade-offs with performance examined through implementation examples.
  • Video and Imaging
  • Where Do We Go From Here?
  • Demonstration: System Generator and the CORE Generator® Tool with a DSP-Targeted Reference DesignTargeted Reference Design Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of Xilinx DSP tools and IP. Reinforce the concepts studied in the course material and exercises.
  • Where Can I Learn More?

Scheduled Classes

Sterling, Virginia
8/14/2019 - 8/14/2019
Columbia, MD
8/21/2019 - 8/21/2019

Education Investment Options

Standard Registration
Standard Registration
18 Training Credits
Advanced Registration
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Engineers and designers who have an interest in developing products that use digital signal processing.


A fundamental understanding of digital signal processing theory, including an understanding of the following principlesSample ratesFinite Impulse Response (FIR) and Infinite Impulse Response (IIR) filtersOscillators and mixersFast Fourier Transform (FFT) algorithm

Software Tools

Vivado System Edition 2012.4Mentor Graphics HyperLynx 8.2.1


Architecture: 7 series FPGAs*Demo board: None** This course focuses on the 7 series FPGA architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Last Updated: 2019-06-06_1626