Designing and Verification with SystemVerilog

This comprehensive course is a thorough introduction to SystemVerilog constructs for design and verification, it is a combination of the instructional material found in Designing with SystemVerilog and Verification with SystemVerilog. This class addresses writing RTL code using the new constructs available in SystemVerilog as well as testbenches to verify your design under test (DUT). New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered in the designing phase of the course. Object-oriented modeling, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered in the verification phase. The information gained can be applied to any digital design and verification flow. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

In this three-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop and verify RTL designs.

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$8979
In-Person Registration - $399/day$119712
Printed Course Book (mailed to you)$1001
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Scheduled Classes

Live Online Training: November 2-4, 2021
Live Online Training: March 15-17, 2022

Training Duration:

3 Days

We update our schedule regularly. Stay informed.

Who should attend:

FPGA designers and logic designers.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the features and benefits of using SystemVerilog for RTL design
  • Identify the new data types supported in SystemVerilog
  • Use an enumerated data type for coding a finite state machine (FSM)
  • Explain how to use structures, unions, and arrays
  • Describe the new procedural blocks and analyze the affected synthesis results
  • Define the enhancements and ability to reuse tasks, functions, and packages
  • Identify how to simplify module definitions and instantiations using interfaces
  • Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
  • Target and optimize Xilinx FPGAs by using SystemVerilog
  • Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
  • Download a complete SystemVerilog design to an evaluation board
  • Describe the advantages and enhancements to SystemVerilog to support verification
  • Discuss and use the various new verification building blocks available in SystemVerilog
  • Describe object-oriented programming and create a class-based verification environment
  • Explain the various methods for creating random data
  • Create and utilize random data for generating stimulus to a DUT
  • Identify how SystemVerilog enhances functional coverage for simulation verification
  • Utilize assertions to quickly identify correct behavior in simulation
  • Identify how the direct programming interface can be used with C/C++ in a verification environment

Course Outline

Day 1Day 2Day 3
  • Introduction to SystemVerilog
  • Data Types
  • Demo: SystemVerilog Integer Data Types
  • LAB: SystemVerilog Data Types
  • Use enumerated data types to build a finite state machine and perform synthesis to analyze the results.
  • Structures, Unions, and Arrays
  • LAB: Structures and Unions
  • Learn about packed and unpacked structures and unions and how to access their members.
  • Additional Operators in System Verilog
  • Procedural Statements and Flow Control
  • LAB: always_ff and always_comb Procedural Blocks
  • Learn to use the new procedural blocks always_comb, always_ff, and always_latch to produce the intended synthesized results.
  • Functions, Tasks, and Packages
  • LAB: Functions, Tasks, and Packages
  • Create a new package and import that package into the module.
  • Interfaces
  • Targeting Xilinx FPGAs
  • LAB: Interfaces and Design Download
  • Use an interface to simplify the module inputs and outputs. Download and verify the design in-circuit.
  • Introduction to SystemVerilog for Verification
  • SystemVerilog Verification Building Blocks
  • LAB: Connecting the Testbench to the DUT
  • Utilize new SystemVerilog verification building blocks to connect the input data to the DUT
  • Object-Oriented Modeling
  • LAB: Object-Oriented Modeling
  • Use object-oriented programming concepts to create a class for enhancing the verification of the DUT
  • Randomization
  • LAB: Randomization
  • Create random data as input into the DUT to fully validate the design.
  • Coverage
  • LAB: Coverage
  • Create and use a coverage group to validate the code coverage for the DUT. Make adjustments and again validate the coverage.
  • Assertions
  • LAB: Assertions
  • Create an assertion to validate all possible conditions are verified for the DUT
  • Direct Programming Interface
  • Demo: Direct Programming Interface
  • Inter Process Communication

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

RELATED COURSES:

Updated 9-02-2021