Designing and Verification with SystemVerilog

COURSE CODE: BLT-SV-DV

This comprehensive course is a thorough introduction to SystemVerilog constructs for design and verification. It is a combination of the instructional material found in Designing with SystemVerilog and Verification with SystemVerilog.

The emphasis is on:

  • Writing RTL code using the new constructs available in SystemVerilog
  • Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
  • Targeting and optimizing AMD FPGAs and adaptive SoC devices using SystemVerilog
  • Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilog
  • Reviewing object-oriented modeling, data types, reusable tasks and functions, randomization, code coverage, assertions, the Direct Programming Interface (DPI), and interprocess communication

In this three-day course, you will gain valuable hands-on experience with practical lab exercises to reinforce key concepts. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop and verify RTL designs.

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

Live Online Training (9am-5pm ET)
View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

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Who should attend:

Hardware designers and engineers, logic designers, and verification engineers.

Software Tools

  • Vivado Design Suite

Hardware

  • Architecture: N/A*
  • Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

* This course does not focus on any particular architecture.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the features and benefits of using SystemVerilog for designing RTL
  • Identify the new data types supported in SystemVerilog
  • Use an enumerated data type for coding a finite state machine (FSM)
  • Explain how to use structures, unions, and arrays
  • Describe the new procedural blocks and analyze the affected synthesis results
  • Define the enhancements and ability to reuse tasks, functions, and packages
  • Identify how to simplify module definitions and instantiations using interfaces
  • Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
  • Target and optimize AMD FPGAs and adaptive SoCs by using SystemVerilog
  • Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
  • Download a complete SystemVerilog design to an evaluation board
  • Describe the advantages and enhancements to SystemVerilog to support verification
  • Define the new data types available in SystemVerilog
  • Analyze and use the improvements to tasks and functions
  • Discuss and use the various new verification building blocks available in SystemVerilog
  • Describe object-oriented programming and create a class-based verification environment
  • Explain the various methods for creating random data
  • Create and utilize random data for generating stimulus to a DUT
  • Identify how SystemVerilog enhances functional coverage for simulation verification
  • Utilize assertions to quickly identify correct behavior in simulation
  • Identify how the direct programming interface can be used with C/C++ in a verification environment
  • Describe the interprocess communication and threads

Course Outline

Day 1Day 2Day 3
Introduction to SystemVerilog
Provides an introduction to the SystemVerilog language. {Lecture}

Data Types
Describes the data types supported by SystemVerilog. {Lecture, Demo, Lab}

User-Defined and Enumerated Data Types
Reviews the user-defined and enumerated data types supported by SystemVerilog. {Lecture}

Type Casting
Explains type casting in SystemVerilog. {Lecture}

Arrays and Strings
Covers the use of arrays in SystemVerilog. {Lecture}

SystemVerilog Building Blocks
Describes the design and verification building blocks in SystemVerilog. {Lecture}

Structures
Illustrates the use of structures in SystemVerilog. {Lecture, Lab}

Unions
Reviews the use of unions in SystemVerilog. {Lecture, Lab}

Additional Operators in SystemVerilog
Describes the operators supported by SystemVerilog beyond those found in Verilog. {Lecture}
Procedural Statements
Highlights the different procedural blocks provided by SystemVerilog. {Lecture, Lab}

Control Flow Statements
Investigates the different control statements provided by SystemVerilog. {Lecture}

Functions
Explains the SystemVerilog enhancements to functions. {Lecture}

Tasks
Describes the task SystemVerilog construct. {Lecture}

Packages
Describes the package SystemVerilog construct. {Lecture, Lab}

Interfaces
Describes the concept of interfaces in SystemVerilog. {Lecture}

Targeting AMD FPGAs and Adaptive SoCs
Focuses on AMD-specific implementation and chip-level optimization. {Lecture, Lab}

Introduction to SystemVerilog for Verification
Provides an introduction to the SystemVerilog language. {Lecture}

Data Types
Explains SystemVerilog data types and arrays, such as fixed-size arrays, dynamic arrays, and associative arrays. {Lecture}
Tasks and Functions
Reviews SystemVerilog tasks and functions {Lecture, Lab}

SystemVerilog Verification Building Blocks
Describes SystemVerilog verification building blocks, such as program, interface, clocking, and packages. {Lecture, Lab}

Object-Oriented Modeling
Introduces object-oriented modeling, such as encapsulation, inheritance, and polymorphism. {Lecture, Lab}

Randomization
 
Illustrates randomization methods, such as randcase, random sequence, and class-based randomization. {Lecture, Lab}

Coverage
Describes functional coverage and usage of covergroup, coverpoint, and bins. {Lecture, Lab}

Assertions
Reviews the different types of assertions. {Lecture, Lab}

Direct Programming Interface
Introduces the Direct Programming Interface (DPI) for interacting with C languages. {Lecture, Demo}

Interprocess Communication
Describes the interprocess communication between the different processes used to model a complex system. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

RELATED COURSES:

Updated 12-18-2023
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