Designing and Verification with SystemVerilog
Designing and Verification with SystemVerilog
This comprehensive course is a thorough introduction to SystemVerilog constructs for design and verification. It is a combination of the instructional material found in Designing with SystemVerilog and Verification with SystemVerilog. This class addresses writing RTL code using the new constructs available in SystemVerilog as well as testbenches to verify your design under test (DUT). New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered in the designing phase of the course. Object-oriented modeling, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered in the verification phase. The information gained can be applied to any digital design and verification flow. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this three-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop and verify RTL designs.
3-Day Instructor-led Course | Price USD | Training Credits |
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Hosted Online - $299/day | $897 | 9 |
In-Person Registration - $399/day | $1197 | 12 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
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Who should attend:
FPGA designers and logic designers.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the features and benefits of using SystemVerilog for RTL design
- Identify the new data types supported in SystemVerilog
- Use an enumerated data type for coding a finite state machine (FSM)
- Explain how to use structures, unions, and arrays
- Describe the new procedural blocks and analyze the affected synthesis results
- Define the enhancements and ability to reuse tasks, functions, and packages
- Identify how to simplify module definitions and instantiations using interfaces
- Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
- Target and optimize Xilinx FPGAs by using SystemVerilog
- Synthesize and analyze SystemVerilog designs with the Vivado™ Design Suite
- Download a complete SystemVerilog design to an evaluation board
- Describe the advantages and enhancements to SystemVerilog to support verification
- Discuss and use the various new verification building blocks available in SystemVerilog
- Describe object-oriented programming and create a class-based verification environment
- Explain the various methods for creating random data
- Create and utilize random data for generating stimulus to a DUT
- Identify how SystemVerilog enhances functional coverage for simulation verification
- Utilize assertions to quickly identify correct behavior in simulation
- Identify how the direct programming interface can be used with C/C++ in a verification environment
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.