Zynq UltraScale+ MPSoC for the Hardware Designer

BLT offers this course under a different name: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

The emphasis is on:

Identifying the key elements of the application processing unit
(APU) and real-time processing unit (RPU)
Reviewing the various power domains and their control structure
Illustrating the processing system (PS) and programmable logic
(PL) connectivity
Utilizing QEMU to emulate hardware behavior

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

See available class dates for Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

Training Duration:

2 Days

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Who should attend:

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.

Skills Gained

After completing this comprehensive training, you will know how to:

Enumerate the key elements of the application processing unit
(APU) and real-time processing unit (RPU)
List the various power domains and how they are controlled
Describe the connectivity between the processing system (PS)
and programmable logic (PL)
Utilize QEMU to emulate hardware behavior

Course Outline

Day 1	Day 2
Application Processing Unit Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed. {Lectures, Lab} HW-SW Virtualization Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used. {Lectures, Demo, Lab} Real-Time Processing Unit Focuses on the real-time processing module (RPU) in the PS, which is comprised of a pair of Cortex processors and supporting elements. {Lectures, Demo, Lab} QEMU Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available. {Lectures, Demos} Booting How to implement the embedded system, including the boot process and boot image creation. {Lectures, Lab} First Stage Boot Loader Demonstrates the process of developing, customizing, and debugging this mandatory piece of code. {Lecture, Demo}	Video Introduction to video, video codecs, and the video codec unit available in the Zynq UltraScale MPSoC. {Lectures} System Protection Covers all the hardware elements that support the separation of software domains. {Lectures} Clocks and Resets Overview of clocking and reset, focusing more on capabilitiesthan specific implementations. {Lectures, Demos} AXI Understanding how the PS and PL connect enables designers to create more efficient systems. {Lectures, Demo, Lab} Power Management Overview of the PMU and the power-saving features of the device. {Lectures, Lab}

Day 1

Day 2

Application Processing Unit

Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed. {Lectures, Lab}

HW-SW Virtualization

Covers the hardware and software elements of virtualization. The
lab demonstrates how hypervisors can be used. {Lectures, Demo, Lab}

Real-Time Processing Unit

Focuses on the real-time processing module (RPU) in the PS,
which is comprised of a pair of Cortex processors and supporting
elements. {Lectures, Demo, Lab}

QEMU

Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available. {Lectures, Demos}

Booting

How to implement the embedded system, including the boot process and boot image creation. {Lectures, Lab}

First Stage Boot Loader

Demonstrates the process of developing, customizing, and debugging this mandatory piece of code. {Lecture, Demo}

Video

Introduction to video, video codecs, and the video codec unit available in the Zynq UltraScale MPSoC. {Lectures}

System Protection

Covers all the hardware elements that support the separation of software domains. {Lectures}

Clocks and Resets

Overview of clocking and reset, focusing more on capabilitiesthan specific implementations. {Lectures, Demos}

AXI

Understanding how the PS and PL connect enables designers to create more efficient systems. {Lectures, Demo, Lab}

Power Management

Overview of the PMU and the power-saving features of the device. {Lectures, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Suggested: Understanding of the Zynq-7000 architecture
Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

RELATED COURSES:

Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC

Updated 3-22-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.