Essential DSP Design Techniques Using System Generator

NOTE: DSP is now taught as DAY 1 in our Vitis Model Composer: A MATLAB and Simulink-based Product. Please view that class for available dates.

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

COURSE CODE: BLT-DSP-SYSGEN

This course provides a foundation for Digital Signal Processing (DSP) techniques for AMD Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced.

Using the System Generator tool to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

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Who should attend:

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB and Simulink software and want to use Xilinx System Generator for DSP design.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the advantages of using FPGAs over traditional processors for DSP designs
Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
Explain the algorithms for video and imaging systems and their implementations in FPGAs
Describe the System Generator design flow for implementing digital signal processing (DSP) functions
Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
List various low-level and high-level functional blocks available in System Generator
Run hardware co-simulation
Identify the high-level blocks available for FIR and FFT designs
Implement multi-rate systems in System Generator
Integrate System Generator models into the Xilinx Vivado® IDE
Design a processor-controllable interface using System Generator for DSP
Generate IPs from C-based design sources for use in the System Generator environment

Course Outline

Day 1	Day 2	Day 3
Back to Basics Architecture FPGA Math LAB: Signed Number Conversion, Quantization and Rounding, Adders, Subtractors, and Accumulation Learn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions. Shift Registers, RAM, and Applications LAB: SRL32E and RAM Estimation and Concatenation Learn how to optimize memory and storage in Xilinx FPGAs. FIR Filter LAB: Filter Implementation, Resource and Performance Estimation Learn how and when to use various implementation strategies for optimal filter implementation. Advanced Filter Techniques LAB: Filter Implementations, Resource and Performance Estimation Advanced filter topologies are studied. Architect multichannel and multirate filters using various methods. Implementation strategies will be discussed and optimal methods used. Fast Fourier Transform LAB: FFT Implementation, Resource and Performance Estimation Select correct parameters for FFT implementations to meet design targets. Resource estimation will be studied and trade-offs with performance examined through implementation examples. Video and Imaging Where Do We Go From Here? Demonstration: System Generator and the CORE Generator Tool with a DSP-Targeted Reference Design Targeted Reference Design Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of Xilinx DSP tools and IP. Reinforce the concepts studied in the course material and exercises. Where Can I Learn More?	Introduction to System Generator Simulink Software Basics LAB: Using the Simulink Software Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate. Basic Xilinx Design Capture Demo: System Generator Gateway Blocks LAB: Getting Started with Xilinx System Generator Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board. Signal Routing LAB: Signal Routing Design padding and unpadding logic by using signal routing blocks. Implementing System Control LAB: Implementing System Control Design an address generator circuit by using blocks and Mcode.	Multi-Rate Systems LAB: Designing a MAC-Based FIR Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board. Filter Design LAB: Designing a FIR Filter Using the FIR Compiler Block Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board. System Generator, Vivado Design Suite, and Vivado HLS Integration LAB: System Generator and Vivado IDE Integration Embed System Generator models into the Vivado IDE. Kintex-7 FPGA DSP Platforms LAB: System Generator and Vivado HLS Tool Integration Generate IP from a C-based design to use with System Generator. LAB: AXI4-Lite Interface Synthesis Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor system.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Experience with the MATLAB and Simulink software
Basic understanding of sampling theory

RELATED COURSES:

Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO

Updated 12-18-2023

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Essential DSP Design Techniques Using System Generator