Designing an Integrated PCI Express System

Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Construct a basic PCIe system by:Selecting the appropriate core for your application, specifying requirements of an endpoint application, connecting this endpoint with the core, utilizing FPGA resources to support the core, simulating the design
  • Identify the advanced capabilities of the PCIe specification protocol and feature set

Course Outline

Day 1

  • Course Introduction
  • Lab 0: Packaet Coding
    This lab helps you recall basic PCI Express transaction layer packet formats.
  • Xilinx PCI Express Solutions
  • Connecting Logic to the Core AXI Interface
  • PCIe Core Customization
  • LAB: Constructing the PCIe Core
    This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
  • Packet Formatting Details
  • Simulating a PCIe System Design
  • LAB: Simulating the PCIe Core
    This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.
  • Endpoint Application Considerations
  • PCI Express in Embedded Systems

Day 2

  • LAB: Using the PCI Express Core in IP Integrator
    This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.
  • Application Focus: DMA
  • Design Implementation and PCIe Configuration
  • LAB: Implementing the PCIe Design
    This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.
  • Root Port Applications
  • Debugging and Compliance
  • LAB: Debugging the PCIe Design
    This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.
  • Interrupts and Error Management
  • Course Summary

Scheduled Classes

Parsippany, NJ
9/10/2019 - 9/11/2019
Trevose, PA
9/10/2019 - 9/11/2019
Hauppauge, NY
9/17/2019 - 9/18/2019
Columbia, MD
9/24/2019 - 9/25/2019
Rochester, NY
10/1/2019 - 10/2/2019
Sterling, Virginia
11/19/2019 - 11/20/2019
Columbia, MD
12/3/2019 - 12/4/2019

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Array

Prerequisites

  • Experience with PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Experience with Xilinx implementation tools
  • Experience with Xilinx timing constraints
  • Experience with Xilinx timing closure
  • Experience with a simulation tool, preferably the Vivado simulator
  • Moderate digital design experience
Version: 2019-08-08_1417