Designing with the Zynq UltraScale+ RFSoC
Designing with the Zynq UltraScale+ RFSoC
This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.
The focus is on:
- Describing the RFSoC family in general
- Identifying applications for the Data Converter and SD-FEC blocks
- Configuring, simulating, and implementing the blocks
- Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes
- Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device
| 2-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $299/day | $598 | 6 |
| In-Person Registration - $399/day | $798 | 8 |
| Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
| Private Training | Contact Us | Contact Us |
| Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
Live Online Training (9am-5pm ET)
The BLT Adaptive Computing Summit
Emerging Solutions for Outer Space, Undersea, and Everywhere in Between
April 25: Columbia, MD • May 2: Melbourne, FL • May 4: Orlando, FL • May 17: Huntsville, AL
Who should attend:
Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ RFSoC data converter and SD-FEC hard blocks.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe in general the new Zynq UltraScale+ RFSoC family
- Identify typical applications for the data converters
- Describe the architecture and functionality of the ADC
- Utilize the ADC via configuration, simulation, and implementation
- Describe the architecture and functionality of the DAC
- Utilize the DAC via configuration, simulation, and implementation
- Identify the requirements and options for data converter PCB designs
- Describe the architecture and functionality of the SD-FEC hard IP
- Utilize the SD-FEC via configuration, simulation, and implementation
Course Outline
Introduction
- Zynq UltraScale+ MPSoC Architectural Overview
- RF Backgrounder
- Zynq UltraScale+ RFSoC Hardware Overview
- Zynq UltraScale+ RFSoC Data Converter Solutions Overview
- Zynq UltraScale+ RFSoC SD-FEC Solutions Overview
- Data Converter Driver Overview
- Zynq UltraScale+ RFSoC ADC-DAC and SD-FEC Tool Support Overview
ADCs
- RF-ADC Basics of ADCs
- RF-ADC Architecture
- RF-ADC Creating ADC System in IPI
- RF-ADC Functionality
- RF-ADC Interfaces
- RF-ADC IP Configuration
- RF-ADC Driver Overview
DACs
- RF-DAC Basics of DACs
- RF-DAC Architecture
- RF-DAC Creating DAC System in IPI
- RF-DAC Functionality
- RF-DAC Interfaces
- RF-DAC IP Configuration
- RF-DAC Driver Overview
Data Converter IP
- Data Converter Common Features
- Data Converter Design Flow
- Data Converter Example Design
- Data Converter Simulation
- Data Converter Implementation
Hardware Requirements
- Zynq® UltraScale+™ RFSoC Power Requirements
- Zynq® UltraScale+™ RFSoC Power Estimation
- Zynq® UltraScale+™ RFSoC Power Design
- Zynq® UltraScale+™ RFSoC Analog Signal Requirements
- Zynq® UltraScale+™ RFSoC PCB Materials and Stackup
- Zynq® UltraScale+™ RFSoC PCB Analog Trace Design
FEC
- SD-FEC Basics of FEC
- SD-FEC IP Architecture and Functionality
- SD-FEC IP Configuration
- SD-FEC IP Interfaces
- SD-FEC Software Driver Overview
- SD-FEC IP Usage
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Suggested: Understanding of the Zynq UltraScale+ MPSoC architecture
- Basic familiarity with data converter terms and principles
- Basic familiarity with forward error correction terms and principles