Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.
The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.
After completing this comprehensive training, you will know how to:
- Write efficient and reusable RTL, testbenches, and packages
- Create self-testing testbenches
- Create realistic models
- Use the text IO capabilities of the VHDL language
- Store simulation data dynamically
- Create parameterized designs
- Create parameterized code for design reuse
- VHDL Overview
- Simulation Concepts
- Advanced Data Types
- Subprograms and Design Attributes
- Lab 1: Flexible Functions
Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
- Access Type Techniques and Blocks
- Lab 2: Linked Lists with Access Types
Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
- Utilizing File IO
- Lab 3: TextIO Techniques
Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
- Advanced Techniques in VHDL
- Lab 4: Creating Real-World Simulations
Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
- Supporting Multiple Platforms
- Lab 5: Supporting Multiple Platforms
Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
- Non-Integer Numbers
- Lab 6: Implementing Fixed and Floating Point Numbers
Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.
- Appendix: Guarded Signals
No Scheduled Sessions - Contact Us to ask about setting one up!
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Who should attend:
VHDL users with intermediate knowledge of VHDL
Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL codingAt least 6 months of coding experience beyond an introductory course
Vivado™ Design or System Edition 2018.1