Advanced VHDL


Increase VHDL proficiency by learning advanced techniques for writing more robust and reusable code.

The focus is on:

  • Writing efficient and reusable RTL, testbenches, and packages
  • Creating self-testing testbenches
  • Creating realistic models
  • Using the text I/O capabilities of the VHDL language
  • Storing simulation data dynamically
  • Creating parameterized code for design reuse

This comprehensive course is targeted toward designers who already have some experience with VHDL.

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$120012
In-Person Public Registration - $600/day$120012
Printed Course Book (A PDF book is included in the course fee)$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

2 Days

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Who should attend:

VHDL users with intermediate knowledge of VHDL.

Software Tools

  • Vivado Design Suite


  • Architecture: N/A*
  • Demo board: None*

* This course does not focus on any particular architecture.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Write efficient and reusable RTL, testbenches, and packages
  • Create self-testing testbenches
  • Create realistic models
  • Use the text IO capabilities of the VHDL language
  • Store simulation data dynamically
  • Create parameterized designs
  • Create parameterized code for design reuse

Course Outline

Day 1Day 2
  • VHDL Overview
  • Simulation Concepts
  • Advanced Data Types
  • Subprograms and Design Attributes
  • LAB: Flexible Functions
    Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
  • Access Type Techniques and Blocks
  • LAB: Linked Lists with Access Types
    Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
  • Utilizing File IO
  • LAB: TextIO Techniques
    Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
  • Advanced Techniques in VHDL
  • LAB: Creating Real-World Simulations
    Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
  • Supporting Multiple Platforms
  • LAB: Supporting Multiple Platforms
    Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
  • Non-Integer Numbers
  • LAB: Implementing Fixed and Floating Point Numbers
    Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.
  • Appendix: Guarded Signals

Please note: The instructor may change the content order to provide a better learning experience.


  • Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding
  • At least 6 months of coding experience beyond an introductory course


Updated 12-18-2023
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