Advanced VHDL

Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.

The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.

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2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

The BLT Adaptive Computing Summit

Emerging Solutions for Outer Space, Undersea, and Everywhere in Between

April 25: Columbia, MD • May 2: Melbourne, FL • May 4: Orlando, FL • May 17: Huntsville, AL

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Who should attend:

VHDL users with intermediate knowledge of VHDL.

Skills Gained

After completing this comprehensive training, you will know how to:

Write efficient and reusable RTL, testbenches, and packages
Create self-testing testbenches
Create realistic models
Use the text IO capabilities of the VHDL language
Store simulation data dynamically
Create parameterized designs
Create parameterized code for design reuse

Course Outline

Day 1	Day 2
VHDL Overview Simulation Concepts Advanced Data Types Subprograms and Design Attributes LAB: Flexible Functions Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports. Access Type Techniques and Blocks LAB: Linked Lists with Access Types Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists. Utilizing File IO LAB: TextIO Techniques Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.	Advanced Techniques in VHDL LAB: Creating Real-World Simulations Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay. Supporting Multiple Platforms LAB: Supporting Multiple Platforms Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes. Non-Integer Numbers LAB: Implementing Fixed and Floating Point Numbers Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models. Appendix: Guarded Signals

Day 1

Day 2

VHDL Overview
Simulation Concepts
Advanced Data Types
Subprograms and Design Attributes
LAB: Flexible Functions
Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
Access Type Techniques and Blocks
LAB: Linked Lists with Access Types
Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
Utilizing File IO
LAB: TextIO Techniques
Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.

Advanced Techniques in VHDL
LAB: Creating Real-World Simulations
Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
Supporting Multiple Platforms
LAB: Supporting Multiple Platforms
Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
Non-Integer Numbers
LAB: Implementing Fixed and Floating Point Numbers
Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.
Appendix: Guarded Signals

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding At least 6 months of coding experience beyond an introductory course

RELATED COURSES:

Updated 3-22-2023

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