High-Level Synthesis with the Vitis HLS Tool
High-Level Synthesis with the Vitis HLS Tool
This is an update to the deprecated course C-based Design: High-Level Synthesis with the Vivado HLx Tool.
Receive a thorough introduction to the AMD Xilinx Vitis™ High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. The course focuses on the Zynq UltraScale+™ MPSoC architecture.
The focus of this course is on:
- Converting C/C++ designs into RTL implementations
- Learning the Vitis HLS tool flow
- Creating I/O interfaces for designs by using the Vitis HLS tool
- Applying different optimization techniques
- Improving throughput, area, latency, and logic by using different HLS pragmas/directives
- Exporting IP that can be used with the Vivado™ IP catalog
- Downloading for in-circuit validation
| 2-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $299/day | $598 | 6 |
| In-Person Registration - $399/day | $798 | 8 |
| Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
| Private Training | Contact Us | Contact Us |
| Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
Live Online Training (9am-5pm ET)
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Who should attend:
Software and hardware engineers looking to utilize high-level synthesis.
Skills Gained
After completing this comprehensive training, you will know how to:
- Enhance productivity using the Vitis HLS tool
- Describe the high-level synthesis flow
- Use the Vitis HLS tool for a first project
- Identify the importance of the test bench
- Use directives to improve performance and area and select RTL interfaces
- Identify common coding pitfalls as well as methods for improving code for RTL/hardware
- Perform system-level integration of IP generated by the Vitis HLS tool
Course Outline
| Day 1 | Day 2 |
|---|---|
| Introduction to High-Level Synthesis Overview of high-level synthesis (HLS), the Vitis HLS tool flow, and the verification advantage. {Lecture} Vitis HLS Tool Flow Explores the basics of high-level synthesis and the Vitis HLS tool. {Lecture, Demo, Lab} Design Exploration with Directives Explores different optimization techniques that can improve the design performance. {Lecture} Vitis HLS Tool Command Line Interface Describes the Vitis HLS tool flow in command prompt mode. {Lecture, Lab} Introduction to Vitis HLS Design Methodology Introduces the methodology guidelines covered in this course and the HLS Design Methodology steps. {Lecture} Introduction to I/O Interfaces Explains interfaces such as the block-level and port-level protocols abstracted by the Vitis HLS tool from the C design. {Lecture} Block-Level Protocols Explains the different types of block-level protocols abstracted by the Vitis HLS tool. {Lecture, Lab} Port-Level I/O Protocols Describes the port-level interface protocols abstracted by the Vitis HLS tool from the C design. {Lecture, Demo, Lab} AXI Adapter Interface Protocols Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS tool. {Lecture, Demo} Port-Level I/O Protocols: Memory Interfaces Describes the memory interface port-level protocols (such as block RAM and FIFO) abstracted by the Vitis HLS tool from the C design. {Lecture, Lab} Pipeline for Performance: PIPELINE Describes the PIPELINE directive for improving the throughput of a design. {Lecture, Lab} | Pipeline for Performance: DATAFLOW Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible. {Lecture, Lab} Optimizing for Throughput Identify the performance limitations caused by arrays in your design. You will also explore optimization techniques to handle arrays for improving performance. {Lecture, Demo, Lab} Optimizing for Latency: Default Behavior Describes the default behavior of the Vitis HLS tool on latency and throughput. {Lecture} Optimizing for Latency: Reducing Latency Describes how to optimize the C design to improve latency. {Lecture} Optimizing for Area and Logic Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. {Lecture, Lab} Migrating to the Vitis HLS Tool Reviews key considerations when moving from the Vivado HLS tool to the Vitis HLS tool. {Lecture} HLS Design Flow – System Integration Describes the traditional RTL flow versus the Vitis HLS tool design flow. {Lecture, Lab} Vitis HLS Tool C++ Libraries: Arbitrary Precision Describes Vitis HLS tool support for the C/C++ languages as well as arbitrary precision data types. {Lecture, Lab} Hardware Modeling Describes hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class. {Lecture} Using Pointers in the Vitis HLS Tool Explains the use of pointers in the design and workarounds for some of the limitations. {Lecture} |
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- C, C++, or System C knowledge
- High-level synthesis for software engineers OR high-level synthesis for hardware engineers