Xilinx Partial Reconfiguration Tools & Techniques

This course demonstrates how to use the Vivado Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment. This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both Ultrascale and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
  • Define PR regions and reconfigurable modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a PR Design
  • Use the ICAP and PCAP components to deliver the Partially Reconfigurable systems
  • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
  • Implement a Partial Reconfiguration system using the following techniques:Direct JTAG connectionFloorplanningTiming constraints and analysis
  • Implement a PR system using the PRC IPImplement a PR system in an embedded environment
  • Debug PR designs

Course Outline

Day 1

  • Introduction to Partial Reconfiguration
  • Demo: Introduction to Partial Reconfiguration
  • Partial Reconfiguration Flow
  • Lab 1: Partial Reconfiguration Tool FlowIllustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
  • Lab 2: Partial Reconfiguration Project FlowIllustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
  • Lab 3: Floorplanning the PR DesignIllustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
  • Partial Reconfiguration Design Considerations
  • Optional: FPGA Configuration Overview
  • Partial Reconfiguration Bitstreams
  • Demo: Partial Reconfiguration Controller (PRC) IP
  • Lab 4: Using the Partial Reconfiguration Controller in a PR DesignIllustrates using the PRC IP and hardware triggers to manage partial bitstreams.

Day 2

  • Partial Reconfiguation: Managing Timing
  • Lab 5: Partial Reconfiguration Timing Analysis and ConstraintsShows how area groups and Reconfigurable Partitions affect design performance.
  • Partial Reconfiguration in Embedded Systems
  • Lab 6: Partial Reconfiguration in Embedded SystemsIllustrates implementing PR designs in an embedded environment.
  • Debugging Partial Reconfiguration Designs
  • Lab 7: Debugging a Partial Reconfiguration DesignDemonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.
  • Partial Reconfiguration Design Recommendations
  • PCIe Core and Partial Reconfiguration

Scheduled Classes

Columbia, MD
8/8/2019 - 8/9/2019
Sterling, Virginia
8/15/2019 - 8/16/2019
Trevose, PA
9/12/2019 - 9/13/2019
Parsippany, NJ
9/12/2019 - 9/12/2019
Hauppauge, NY
9/19/2019 - 9/20/2019
Rochester, NY
10/3/2019 - 10/4/2019
Sterling, Virginia
11/21/2019 - 11/22/2019

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques.

Prerequisites

Vivado Boot Camp Phase-1: Designing for Performance Vivado Boot Camp Phase-2: Implementing for PerformancecourseVivado Boot Camp Phase-3: Achieving Performancecourse

Working HDL knowledge (Designing with VHDL or Designing with Verilog)

Software Tools

Vivado Design or System Edition 2017.1 with PR license

Hardware

Architecture: Ultrascale and 7 series FPGAs*Demo board: Kintex Ultrascale FPGA KCU105 board, Kintex-7 FPGA KC705 board, and ZedBoard*** This course focuses on the Ultrascale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.** The Ultrascale architecture versions of the "Using the PRC IP in a Partial Reconfiguration Design" lab and the "Using ILA Cores to Debug Partial Reconfiguration Designs" lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The "Partial Reconfiguration in Embedded Systems" lab requires a ZedBoard for implementation.

Last Updated: 2019-06-06_1626