Xilinx Partial Reconfiguration Tools & Techniques
Xilinx Partial Reconfiguration Tools & Techniques
This course is now being offered under a different name. Please view it here.
This partial reconfiguration course demonstrates how to use the Xilinx® Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.
This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.
2-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $299/day | $598 | 6 |
In-Person Registration - $399/day | $798 | 8 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
See available class dates for Dynamic Function eXchange (DFX) Using the Vivado Design Suite.
Training Duration:
2 Days
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Who should attend:
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques.
Skills Gained
After completing this comprehensive training, you will know how to:
- Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
- Define PR regions and reconfigurable modules with the Vivado Design Suite
- Generate the appropriate full and partial bitstreams for a PR Design
- Use the ICAP and PCAP components to deliver the Partially Reconfigurable systems
- Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
- Implement a Partial Reconfiguration system using the following techniques: Direct JTAG connection, Floorplanning, Timing constraints and analysis
- Implement a PR system using the PRC IP
- Implement a PR system in an embedded environment
- Debug PR designs
Course Outline
Day 1 | Day 2 |
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO
- Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging
- Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure
- Working HDL knowledge (Designing with VHDL or Designing with Verilog)
RELATED COURSES:
- Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials – Architecture, Memory and IO
- Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging
- Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure
- Designing with VHDL
- Designing with Verilog