Xilinx Partial Reconfiguration Tools & Techniques

This course demonstrates how to use the Vivado Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.

This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
  • Define PR regions and reconfigurable modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a PR Design
  • Use the ICAP and PCAP components to deliver the Partially Reconfigurable systems
  • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
  • Implement a Partial Reconfiguration system using the following techniques:Direct JTAG connection, Floorplanning, Timing constraints and analysis
  • Implement a PR system using the PRC IP
  • Implement a PR system in an embedded environment
  • Debug PR designs

Course Outline

Day 1

  • Introduction to Partial Reconfiguration
  • Demo: Introduction to Partial Reconfiguration
  • Partial Reconfiguration Flow
  • LAB: Partial Reconfiguration Tool Flow
    Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
  • LAB: Partial Reconfiguration Project Flow
    Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
  • LAB: Floorplanning the PR Design
    Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
  • Partial Reconfiguration Design Considerations
  • Optional: FPGA Configuration Overview
  • Partial Reconfiguration Bitstreams
  • Demo: Partial Reconfiguration Controller (PRC) IP
  • LAB: Using the Partial Reconfiguration Controller in a PR Design
    Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.

Day 2

  • Partial Reconfiguation: Managing Timing
  • LAB: Partial Reconfiguration Timing Analysis and Constraints
    Shows how area groups and Reconfigurable Partitions affect design performance.
  • Partial Reconfiguration in Embedded Systems
  • LAB: Partial Reconfiguration in Embedded Systems
    Illustrates implementing PR designs in an embedded environment.
  • Debugging Partial Reconfiguration Designs
  • LAB: Debugging a Partial Reconfiguration Design
    Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.
  • Partial Reconfiguration Design Recommendations
  • PCIe Core and Partial Reconfiguration

Scheduled Classes

Sterling, Virginia
11/21/2019 – 11/22/2019

Columbia, MD
12/5/2019 – 12/6/2019

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.

To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques.

Prerequisites

Version: 2019-10-07_1352