Accelerating Applications with the Vitis Unified Software Environment

Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis unified software environment targeting both data center (DC) and embedded applications. Also learn how to run designs on the Xilinx Alveo accelerator card using Nimbix Cloud.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe how the FPGA architecture lends itself to parallel computing
  • Explain how the Vitis unified software environment helps software developers to focus on applications
  • Describe the Vitis (OpenCL API) execution model
  • Analyze the OpenCL API memory model
  • Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard
  • Apply host code optimization and kernel optimization techniques
  • Move data efficiently between kernel and global memory
  • Profile the design using the Vitis analyzer tool

Learn more about the Xilinx Vitis Unified Platform.

Course Outline

Day 1

  • Introduction to the Vitis Unified Software Platform {Lecture}
  • Vitis IDE Tool Overview {Lecture, Labs}
  • Vitis Command Line Flow {Lecture, Labs}
  • Introduction to Hardware Acceleration {Lecture}
  • Alveo Data Center Accelerator Cards Overview {Lecture}
  • Alveo Accelerator Card Ecosystem Partner Solutions Overview (Optional) {Lecture}
  • Getting Started with Alveo Data Center Accelerator Cards {Lecture}
  • Introduction to the Nimbix Cloud {Lecture}
  • Xilinx Real-Time Video Server Appliance (Optional) {Lecture}
  • Vitis Execution Model and XRT {Lecture, Lab}
  • Synchronization {Lecture, Lab}
  • Xilinx Card Utilities {Lecture}

Day 2

  • Introduction to NDRanges {Lecture}
  • Working with NDRanges {Lecture}
  • Profiling {Lecture}
  • Debugging {Lecture}
  • Introduction to C/C++ based Kernels {Lecture, Lab}
  • Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab}
  • Optimization Methodology {Lecture}
  • C/C++ based Kernel Optimization {Lecture}
  • Host Code Optimization {Lecture}
  • Optimizing the Performance of the Design {Lab}
  • Vitis Accelerated Libraries {Lecture}
  • Creating a Vitis Embedded Acceleration Platform (Edge) {Lecture}

No Scheduled Sessions – Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.

REGISTER

Training Duration:

2 Days

Who should attend:

Anyone who needs to accelerate their software applications using FPGAs, SoCs (such as Zynq®-7000 SoCs, Zynq® UltraScale+ MPSoCs), and Versal ACAPs

Prerequisites:

  • Basic knowledge of Xilinx FPGA architecture
  • Comfort with the C/C++ programming language
  • Software development flow

Version: 2021-03-17_0932