Accelerating Applications with the Vitis Unified Software Environment

Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis^™ unified software environment targeting both data center (DC) and embedded applications. Also learn how to run designs on the Xilinx® Alveo^™ accelerator card using Nimbix Cloud.

Learn more about the Xilinx Vitis Unified Platform.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$598	6
In-Person Registration - $399/day	$798	8
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

The BLT Adaptive Computing Summit

Emerging Solutions for Outer Space, Undersea, and Everywhere in Between

April 25: Columbia, MD • May 2: Melbourne, FL • May 4: Orlando, FL • May 17: Huntsville, AL

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Who should attend:

Anyone who needs to accelerate their software applications using FPGAs, SoCs (such as Zynq^®-7000 SoCs, Zynq^® UltraScale+^™ MPSoCs), and Versal^® ACAPs.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe how the FPGA architecture lends itself to parallel computing
Explain how the Vitis unified software environment helps software developers to focus on applications
Describe the Vitis (OpenCL API) execution model
Analyze the OpenCL API memory model
Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard
Apply host code optimization and kernel optimization techniques
Move data efficiently between kernel and global memory
Profile the design using the Vitis analyzer tool

Course Outline

Day 1	Day 2
Introduction to the Vitis Unified Software Platform {Lecture} Vitis IDE Tool Overview {Lecture, Labs} Vitis Command Line Flow {Lecture, Labs} Introduction to Hardware Acceleration {Lecture} Alveo Data Center Accelerator Cards Overview {Lecture} Alveo Accelerator Card Ecosystem Partner Solutions Overview (Optional) {Lecture} Getting Started with Alveo Data Center Accelerator Cards {Lecture} Introduction to the Nimbix Cloud {Lecture} Xilinx Real-Time Video Server Appliance (Optional) {Lecture} Vitis Execution Model and XRT {Lecture, Lab} Synchronization {Lecture, Lab} Xilinx Card Utilities {Lecture}	Introduction to NDRanges {Lecture} Working with NDRanges {Lecture} Profiling {Lecture} Debugging {Lecture} Introduction to C/C++ based Kernels {Lecture, Lab} Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab} Optimization Methodology {Lecture} C/C++ based Kernel Optimization {Lecture} Host Code Optimization {Lecture} Optimizing the Performance of the Design {Lab} Vitis Accelerated Libraries {Lecture} Creating a Vitis Embedded Acceleration Platform (Edge) {Lecture}

Day 1

Day 2

Introduction to the Vitis Unified Software Platform {Lecture}
Vitis IDE Tool Overview {Lecture, Labs}
Vitis Command Line Flow {Lecture, Labs}
Introduction to Hardware Acceleration {Lecture}
Alveo Data Center Accelerator Cards Overview {Lecture}
Alveo Accelerator Card Ecosystem Partner Solutions Overview (Optional) {Lecture}
Getting Started with Alveo Data Center Accelerator Cards {Lecture}
Introduction to the Nimbix Cloud {Lecture}
Xilinx Real-Time Video Server Appliance (Optional) {Lecture}
Vitis Execution Model and XRT {Lecture, Lab}
Synchronization {Lecture, Lab}
Xilinx Card Utilities {Lecture}

Introduction to NDRanges {Lecture}
Working with NDRanges {Lecture}
Profiling {Lecture}
Debugging {Lecture}
Introduction to C/C++ based Kernels {Lecture, Lab}
Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab}
Optimization Methodology {Lecture}
C/C++ based Kernel Optimization {Lecture}
Host Code Optimization {Lecture}
Optimizing the Performance of the Design {Lab}
Vitis Accelerated Libraries {Lecture}
Creating a Vitis Embedded Acceleration Platform (Edge) {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of Xilinx FPGA architecture
Comfort with the C/C++ programming language
Software development flow

RELATED COURSES:

Updated 3-22-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.