Vivado Design Suite for ISE Software Project Navigator Users

This course offers introductory training on the Vivado Design Suite. This course is for experienced ISE software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing closure
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

Day 1

  • UltraFast® Design Methodology: PlanningIntroduces the methodology guidelines on planning and the UltraFast® Design Methodology checklist.
  • UltraFast® Design Methodology: Design Creation and AnalysisOverview of the methodology guidelines on design creation and analysis.
  • HDL Coding TechniquesCovers basic digital coding guidelines used in an FPGA design.
  • ResetsInvestigates the impact of using asynchronous resets in a design.
  • Register DuplicationUse register duplication to reduce high fanout nets in a design.
  • Synchronous Design TechniquesIntroduces synchronous design techniques used in an FPGA design.
  • Introduction to the Vivado Design SuiteIntroduces the Vivado Design Suite.
  • Introduction to Vivado Design FlowsIntroduces the Vivado design flows: the project flow and non-project batch flow.
  • Vivado Design Suite Project ModeCreate a project, add files to the project, explore the Vivado IDE, and simulate the design.
  • Synthesis and Implementation

Day 2

  • Vivado IP FlowCustomize IP, instantiate IP, and verify the hierarchy of your design IP.
  • Designing with IP IntegratorUse the Vivado IP integrator to create the uart_led subsystem.
  • Vivado Design Suite Non-Project ModeCreate a design in the Vivado Design Suite non-project mode.
  • Introduction to the Tcl EnvironmentIntroduces Tcl (tool command language).
  • Design Analysis Using Tcl CommandsAnalyze a design using Tcl commands.
  • Scripting in Vivado Design Suite Project ModeExplains how to write Tcl commands in the project-based flow for a design.
  • Scripting in Vivado Design Suite Non-Project ModeWrite Tcl commands in the non-project batch flow for a design.

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,600
Standard Registration
16 Training Credits
Advanced Registration
$1,400
Advanced Registration
14 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$700
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Existing Xilinx ISE software Project Navigator FPGA designers

Prerequisites

Basic knowledge of the VHDL or Verilog language

Digital design knowledge

Software Tools

Vivado System Edition 2017.1

Hardware

Architecture: Ultrascale and 7 series FPGAs*Demo board (optional): Kintex Ultrascale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board** This course focuses on the Ultrascale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626