Vivado Design Suite for ISE Software Project Navigator Users

This course offers introductory training on the Vivado Design Suite. This course is for experienced ISE software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing closure
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

Day 1

  • UltraFast® Design Methodology: Planning
    Introduces the methodology guidelines on planning and the UltraFast® Design Methodology checklist.
  • UltraFast® Design Methodology: Design Creation and Analysis
    Overview of the methodology guidelines on design creation and analysis.
  • HDL Coding Techniques
    Covers basic digital coding guidelines used in an FPGA design.
  • Resets
    Investigates the impact of using asynchronous resets in a design.
  • Register Duplication
    Use register duplication to reduce high fanout nets in a design.
  • Synchronous Design Techniques
    Introduces synchronous design techniques used in an FPGA design.
  • Introduction to the Vivado Design Suite
    Introduces the Vivado Design Suite.
  • Introduction to Vivado Design Flows
    Introduces the Vivado design flows: the project flow and non-project batch flow.
  • Vivado Design Suite Project Mode
    Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
  • Synthesis and Implementation
    Create timing constraints according to the design scenario and synthesize and implement the design.
  • Basic Design Analysis in the Vivado IDE
    Use the various design analysis features in the Vivado Design Suite.
  • Vivado Design Suite I/O Pin Planning
    Use the I/O Pin Planning layout to perform pin assignments in a design.

Day 2

  • Vivado IP Flow
    Customize IP, instantiate IP, and verify the hierarchy of your design IP.
  • Designing with IP Integrator
    Use the Vivado IP integrator to create the uart_led subsystem.
  • Vivado Design Suite Non-Project Mode
    Create a design in the Vivado Design Suite non-project mode.
  • Introduction to the Tcl Environment
    Introduces Tcl (tool command language).
  • Design Analysis Using Tcl Commands
    Analyze a design using Tcl commands.
  • Scripting in Vivado Design Suite Project Mode
    Explains how to write Tcl commands in the project-based flow for a design.
  • Scripting in Vivado Design Suite Non-Project Mode
    Write Tcl commands in the non-project batch flow for a design.

No Scheduled Sessions – Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$1,800
Standard Registration
18 Training Credits
Advanced Registration
$1,600
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.

To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Existing Xilinx ISE software Project Navigator FPGA designers

Prerequisites

  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge

Version: 2019-10-07_1352