Designing with Xilinx Serial Transcievers

In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale, Ultrascale+ FPGA or Zynq® Ultrascale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
  • Effectively utilize the following features of the gigabit transceivers:64B/66B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and receive equalization
  • Use the Transceivers Wizards to instantiate GT primitives in a design
  • Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
  • Use the IBERT design to verify transceiver links on real hardware

Course Outline

Day 1

  • 7 Series, UltraScale, Ultrascale+, Zynq® Ultrascale+ Transceivers Overview
  • 7 Series, UltraScale, Ultrascale+, Zynq® Ultrascale+ Transceivers Clocking and Resets
  • Transceiver IP Generation Transceiver Wizard
  • Lab 1: Transceiver Core GenerationUse the Transceivers Wizard to create instantiation templates.
  • Transceiver Simulation
  • Lab 2: Transceiver SimulationSimulate the transceiver IP by using the IP example design.
  • PCS Layer General Functionality
  • PCS Layer Encoding
  • Lab 3: 64B/66B EncodingGenerate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.

Day 2

  • Transceiver Implementation
  • Lab 4: Transceiver ImplementationImplement the transceiver IP by using the IP example design.
  • PMA Layer Details
  • PMA Layer Optimization
  • Lab 5: IBERT DesignVerify transceiver links on real hardware.
  • Transceiver Test and Debugging
  • Lab 6: Transceiver DebuggingDebug transceiver links.
  • Transceiver Board Design Considerations
  • Transceiver Application Examples

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
Standard Registration
18 Training Credits
Advanced Registration
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

FPGA designers and logic designers


Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL courseFamiliarity with logic design (state machines and synchronous design)Basic knowledge of FPGA architecture and Xilinx implementation tools are helpfulFamiliarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools

Vivado System Edition 2016.3Mentor Graphics Questa Advanced Simulator 10.4


Architecture: 7 series and Ultrascale FPGAs*Demo board: Kintex Ultrascale FPGA KCU105 board or Kintex-7 FPGA KC705 board** This course focuses on the Ultrascale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626