Designing with Xilinx Serial Transceivers

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Designing with Xilinx Serial Transceivers

BLT offers a newer course for this material: Designing an Integrated PCI Express System with Xilinx Serial Transceivers

In this two-day course, you will learn how to employ Xilinx® serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+™ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.

Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.

Learn more about Xilinx serial transceivers.

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$5986
In-Person Registration - $399/day$7988
Printed Course Book (A PDF book is included in the course fee)$1001
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Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

2 Days

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Who should attend:

FPGA designers and logic designers.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
  • Effectively utilize the following features of the gigabit transceivers:64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding, pre-emphasis and receive equalization
  • Use the Transceivers Wizards to instantiate GT primitives in a design
  • Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
  • Use the IBERT design to verify transceiver links on real hardware

Course Outline

Day 1Day 2
  • 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview
  • 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets
  • Transceiver IP Generation Transceiver Wizard
  • LAB: Transceiver Core Generation
    Use the Transceivers Wizard to create instantiation templates.
  • Transceiver Simulation
  • LAB: Transceiver Simulation
    Simulate the transceiver IP by using the IP example design.
  • PCS Layer General Functionality
  • PCS Layer Encoding
  • LAB: 64B/66B Encoding
    Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.
  • Transceiver Implementation
  • LAB: Transceiver Implementation
    Implement the transceiver IP by using the IP example design.
  • PMA Layer Details
  • PMA Layer Optimization
  • LAB: IBERT Design
    Verify transceiver links on real hardware.
  • Transceiver Test and Debugging
  • LAB: Transceiver Debugging
    Debug transceiver links.
  • Transceiver Board Design Considerations
  • Transceiver Application Examples

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
  • Familiarity with logic design (state machines and synchronous design)
  • Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

RELATED COURSES:

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Updated 3-22-2023
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