Course Index
COMPLETE COURSE LIST
| Course | Common Topics | Persona | Silicon | Status |
|---|---|---|---|---|
| Designing with the Versal ACAP: Architecture and Methodology | Architecture, Tools, Simulation, Debugging, Versal, PetaLinux | Hardware Engineer, Software Engineer, System Architect | FPGA, ACAP, SoC | Current |
| Using Vision-based Applications with the Kria SOM | Architecture, Tools, AI | Hardware Engineer, Software Engineer | FPGA, SOM, SoC, AI | Current |
| Designing with the Versal ACAP: Network on Chip | Architecture, Versal, Memory, I/O, Debugging | Hardware Engineer, Software Engineer, System Architect | ACAP | Current |
| Designing with the Versal ACAP: Power and Board | Signal Integrity, Versal, Power | Hardware Engineer, System Architect | ACAP | Current |
| Designing with Versal AI Engine 1: Architecture and Design Flow | Versal, Architecture, Tools, Embedded | Hardware Engineer, Software Engineer, System Architect | ACAP, AI | Current |
| Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | Versal, Tools, Debugging, Embedded | Software Engineer, System Architect | ACAP, AI | Current |
| Designing with Versal AI Engine 3: Kernel Programming and Optimization | Versal, Debugging, Embedded | Software Engineer, System Architect | ACAP, AI | Current |
| Vitis Model Composer: A MATLAB and Simulink-based Product | Vitis, DSP, HLS, AI, MATLAB | Hardware Engineer, System Architect | FPGA, ACAP, AI | Current |
| Accelerating Applications with the Vitis Unified Software Environment | Tools, Vitis, Embedded | Software Engineer, System Architect | FPGA, ACAP, SoC, AI | Current |
| Developing AI Inference Solutions with the Vitis AI Platform | Vitis, ML | Software Engineer | AI | Current |
| BLT Exclusive: Embedded Systems Hardware Design Boot Camp | Vivado, MPSoC, Zynq UltraScale+, Debugging, Tools | Hardware Engineer, Software Engineer, System Architect | SoC | Current |
| BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials - Architecture, Memory and IO | Architecture, Memory, I/O, Clocking, Ultrascale, Tools | Hardware Engineer | FPGA | Current |
| BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging | Vivado, Tcl, Tools, Clocking, Debugging, Timing Constraints, Simulation | Hardware Engineer | FPGA | Current |
| BLT Exclusive: Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure | Vivado, Timing Constraints, Clocking, Debugging | Hardware Engineer | FPGA | Current |
| BLT Exclusive: Vivado Boot Camp: Basic Training | Architecture, Vivado, Tools, Timing Constraints | Hardware Engineer | FPGA | Current |
BLT Exclusive: Spartan-6 / ISE User Migration Training | Vivado, Tcl, Tools, Clocking, Debugging, Timing Constraints, Simulation | Hardware Engineer | FPGA | Current |
| BLT Exclusive: Designing an Integrated PCI Express System with Xilinx Serial Transceivers | Connectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIe, Embedded, Signal Integrity | Hardware Engineer, System Architect | FPGA | Deprecated |
BLT Exclusive: Advanced Debug Techniques for Hardware Engineers | Debugging, Vivado, Tools | Hardware Engineer, System Architect | FPGA, SoC | Current |
BLT Exclusive: Advanced Debugging Workshop (Sponsored by AMD - Xilinx) | Debugging, Vivado, Tools, Spartan-6 Migration | Hardware Engineer, System Architect | FPGA, SoC | Current |
| Designing an Integrated PCI Express System | Connectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIe | Hardware Engineer, Software Engineer, System Architect | FPGA | Current |
| Design Closure Techniques | FPGA, Vivado, Timing Closure, Test Bench, Simulation, Design Closure | Hardware Engineer, Software Engineer, System Architect | FPGA, ACAP | Current |
| Designing with UltraScale FPGA Transceivers | Signal Integrity, Testbench, Debugging | Hardware Engineer | FPGA | Current |
| Designing with Xilinx Serial Transcievers | Signal Integrity, Testbench, Debugging | Hardware Engineer | FPGA | Current |
| Dynamic Function eXchange (DFX) Using the Vivado Design Suite | Tools, Debugging, partial reconfiguration | Hardware Engineer | FPGA | Current |
| Signal Integrity and Board Design for Xilinx FPGAs | Signal Integrity, Clocking, Simulation, Verification | Hardware Engineer | FPGA | Current |
| BLT Exclusive: Essential DSP Design Techniques using System Generator | DSP, Tools, Verification, Simulation | Hardware Engineer, System Architect | FPGA | Deprecated |
| DSP Design Using System Generator | DSP, Tools, Verification, Simulation | Hardware Engineer, System Architect | FPGA | Deprecated |
| Essential DSP Implementation Techniques for Xilinx FPGAs | DSP, Tools, Verification, Simulation | Hardware Engineer, System Architect | FPGA | Current |
| Designing FPGAs Using the Vivado Design Suite 1 | Architecture, Vivado, Timing Constraints, Debugging, Tools, Clocking, Tcl | Hardware Engineer | FPGA | Current |
| Designing FPGAs Using the Vivado Design Suite 2 | Vivado, Debugging, Tcl, Timing Constraints, Clocking | Hardware Engineer | FPGA | Current |
| Designing FPGAs Using the Vivado Design Suite 3 | Debugging, Timing Constraints, Vivado, Clocking, Tcl | Hardware Engineer | FPGA | Current |
| Designing FPGAs Using the Vivado Design Suite 4 | Debugging, Timing Constraints, Vivado, Clocking, Tcl | Hardware Engineer | FPGA | Current |
| Xilinx Partial Reconfiguration Tools & Techniques | Tools, Debugging, Partial Reconfiguration | Hardware Engineer | FPGA | Current |
| Designing with the UltraScale and UltraScale+ Architectures | UltraScale+, UltraScale, Architecture, Clocking, DSP | Hardware Engineer, System Architect | FPGA | Current |
| Advanced VHDL | RTL, Testbench, Simulation, Language | Hardware Engineer, System Architect | FPGA, SoC | Current |
| BLT Exclusive: Designing and Verification with SystemVerilog | RTL, Testbench, Simulation, Language, Verification | Hardware Engineer, System Architect | FPGA | Current |
| Designing with SystemVerilog | RTL, Language | Hardware Engineer, System Architect | FPGA | Current |
| Designing with Verilog | RTL, Testbench, Simulation, Language | Hardware Engineer, System Architect | FPGA | Current |
| Designing with VHDL | RTL, Testbench, Simulation, Language | Hardware Engineer, System Architect | FPGA | Current |
| Verification with SystemVerilog | RTL, Language | Hardware Engineer, System Architect | FPGA | Current |
| High-Level Synthesis with the Vitis HLS Tool | Vitis, Tools, Testbench, Zynq UltraScale+, MPSoC, RTL, HLS | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Current |
| Designing with the Zynq UltraScale+ RFSoC | RFSoC, Simulation, Zynq UltraScale+ | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Current |
| Embedded Design with PetaLinux Tools | Zynq UltraScale+, MPSoC, Versal, Embedded, Tools, Debugging | Software Engineer, System Architect | SoC | Current |
| Zynq UltraScale+ MPSoC for the Hardware Designer | Zynq UltraScale+, MPSoC, Tools, Vivado | Hardware Engineer | FPGA, SoC | Current |
| Zynq UltraScale+ MPSoC for the Software Developer | Zynq UltraScale+, MPSoC, Embedded, Tools, Debugging | Software Engineer | SoC | Current |
| Zynq UltraScale+ MPSoC for the System Architect | Zynq UltraScale+, MPSoC, Embedded, Tools, Debugging | System Architect | FPGA, SoC | Current |
| Xilinx for Managers | Architecture, Tools, Methodologies | Manager | FPGA, SoC, ACAP | Current |
| PCIe Protocol Overview | PCIe, Debugging, Embedded, Connectivity | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
C-based Design: High-Level Synthesis with the Vivado HLx Tool | Vitis, Tools, Testbench, RTL, HLS | Hardware Engineer, Software Engineer, System Architect | FPGA | Deprecated |
| Designing with the Xilinx 7 Series Families | Architecture, Clocking, DSP | Hardware Engineer, System Architect | FPGA, SoC | Deprecated |
| Developing and Optimizing Applications Using the OpenCL Framework for FPGAs | OpenCL, Debugging, Embedded | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Embedded Systems Design | Embedded, Zynq, Vivado, Tools, Simulation | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Embedded Systems Software Design | Embedded, Zynq, Vivado, Tools, Debugging | Software Engineer | SoC | Deprecated |
| How to Design a High-Speed Memory Interface | Memory, I/O, Debugging, Tools, Testbench | Hardware Engineer | FPGA | Deprecated |
| Migrating to the Vitis Embedded Software Development IDE Workshop | Vitis, Tools, Debugging, Embedded | Hardware Engineer, Software Engineer, System Architect | SoC | Deprecated |
| UltraFast Design Methodology | Vivado, Tools, Timing Constraints, I/O | Hardware Engineer, System Architect | FPGA | Deprecated |
| Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users | Vivado, Tools, Timing Constraints, Tcl | Hardware Engineer | FPGA | Deprecated |
| Vivado Design Suite for ISE Software Project Navigator Users | Vivado, Tools, Simulation, Timing Constraints | Hardware Engineer | FPGA | Deprecated |
| Zynq All Programmable SoC System Architecture | Zynq, Memory, I/O, Architecture | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Advanced Features and Techniques of Embedded Systems Design | Embedded, Vivado, Simulation, Verification | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Advanced SDSoC Development Environment and Methodology | Architecture, Memory, Vivado, Tools | Hardware Engineer, Software Engineer, System Architect | SoC | Deprecated |
| Designing with Ethernet MAC Controllers | Ethernet, Simulation, Vivado, Testbench, I/O | Hardware Engineer | FPGA | Deprecated |
| Designing with the Spartan-6 and Virtex-6 FPGA Families | Architecture, Spartan-6, Vivado, Tools, Clocking | Hardware Engineer, System Architect | FPGA | Deprecated |
| Design Closure, Timing Closure, Simulation, Verification | Software Developer, Hardware Engineer, System Architect | FPGA, SoC, ACAP | Current |
A lot of insights beyond the course
Glenn was a great instructor and provided us with a lot of insights beyond the course material
– Student from Embedded Design with PetaLinux Tools
College course fit into 3 days
The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.
– Student from Designing with VDHL
One of the best experiences for AMD Xilinx training that I’ve had
Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.
– Student from Designing with VHDL
I gained a lot of information
The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!
– Student from Vivado Boot Camp for the FPGA User Phase 1
Can quickly and concisely answer technical questions
I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!
– Student from Vivado Boot Camp for the FPGA User Phase 3
I would endorse him to teach a friend
Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.
– Student from Designing with Verilog
Expert tidbits
I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.
– Student from Designing with VHDL
Labs were great
The labs were great and really reinforced the topics.
– Student from Designing with Versal AI Engine 1: Architecture and Design Flow
The instructor was excellent
The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.
– Student from Embedded Design with PetaLinux Tools
All in all a great experience
Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.
– Student from Vivado Boot Camp for the FPGA User Phase 2
This one was definitely one of the best
I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!
– Student from Vivado Boot Camp for the FPGA User Phase 1
Elie was an exceptional instructor
Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.
– Student from Designing with Verilog
Thanks for a great class!
I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!
– Student from Vivado Boot Camp for the FPGA User Phase 1
I had a wonderful instructor
I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.
– Student from Vivado Boot Camp for the FPGA User Phase 3
Erich was engaging
Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.
– Student from Vivado Boot Camp for the FPGA User Phase 1
Impressed with the effort
Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.
– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization
They had answers for just about every question
Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.
– Student from Vivado Boot Camp for the FPGA User Phase 2
Knowledgeable instructor
Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.
– Student from Designing with VHDL
My instructor was very professional
My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.
– Student from Vivado Boot Camp for the FPGA User Phase 1
My instructor took time
My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.
– Student from Vivado Boot Camp for the FPGA User Phase 3
My instructor was very capable
My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question
– Student from Vivado Boot Camp for the FPGA User Phase 1