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COMPLETE COURSE LIST

This list includes all courses offered by BLT, including AMD Courses and BLT Custom Courses. Courses listed as “Public” in Availability are currently listed on our Calendar of classes.

CourseCommon TopicsPersonaSiliconStatusAvailability*
Accelerating Applications with the Vitis Unified Software EnvironmentTools, Vitis, EmbeddedSoftware Engineer, System ArchitectFPGA, Adaptive SoC, SoC, AICurrentPrivate Only
Adaptive Computing for ManagersArchitecture, Tools, MethodologiesManagerFPGA, SoC, Adaptive SoCCurrentPublic and Private
Adaptive SoCs for System ArchitectsEmbedded, Power, DebuggingSystem ArchitectAdaptive SoC, SoCCurrentComing soon
Advanced Debug Techniques for Hardware Engineers (BLT Exclusive)Debugging, Vivado, ToolsHardware Engineer, System ArchitectFPGA, SoCCurrentPrivate Only
Advanced Features and Techniques of Embedded Systems DesignEmbedded, Vivado, Simulation, VerificationHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecatedPrivate Only
Advanced SDSoC Development Environment and MethodologyArchitecture, Memory, Vivado, ToolsHardware Engineer, Software Engineer, System ArchitectSoCDeprecatedPrivate Only
Advanced VHDLRTL, Testbench, Simulation, LanguageHardware Engineer, System ArchitectFPGA, SoCCurrentPrivate Only

C-based Design: High-Level Synthesis with the Vivado HLx Tool

Vitis, Tools, Testbench, RTL, HLSHardware Engineer, Software Engineer, System ArchitectFPGADeprecatedPrivate Only
Design Closure TechniquesFPGA, Vivado, Timing Closure, Test Bench, Simulation, Design ClosureHardware Engineer, Software Engineer, System ArchitectFPGA, Adaptive SoCCurrentPublic and Private
Designing an Integrated PCI Express SystemConnectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIeHardware Engineer, Software Engineer, System ArchitectFPGACurrentPrivate Only
Designing an Integrated PCI Express System with Xilinx Serial Transceivers (BLT Exclusive)Connectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIe, Embedded, Signal IntegrityHardware Engineer, System ArchitectFPGADeprecatedPrivate Only
Designing and Verification with SystemVerilog (BLT Exclusive)RTL, Testbench, Simulation, Language, VerificationHardware Engineer, System ArchitectFPGACurrentPublic and Private
Designing FPGAs Using the Vivado Design Suite 1Architecture, Vivado, Timing Constraints, Debugging, Tools, Clocking, TclHardware EngineerFPGACurrentPublic and Private
Designing FPGAs Using the Vivado Design Suite 2Vivado, Debugging, Tcl, Timing Constraints, ClockingHardware EngineerFPGACurrentPublic and Private
Designing FPGAs Using the Vivado Design Suite 3Debugging, Timing Constraints, Vivado, Clocking, TclHardware EngineerFPGACurrentPublic and Private
Designing FPGAs Using the Vivado Design Suite 4Debugging, Timing Constraints, Vivado, Clocking, TclHardware EngineerFPGACurrentPublic and Private
Designing with Ethernet MAC ControllersEthernet, Simulation, Vivado, Testbench, I/OHardware EngineerFPGADeprecatedPrivate Only
Designing with SystemVerilogRTL, LanguageHardware Engineer, System ArchitectFPGACurrentPrivate Only
Designing with the IP Integrator ToolCurrentPrivate Only
Designing with the Spartan-6 and Virtex-6 FPGA FamiliesArchitecture, Spartan-6, Vivado, Tools, Clocking Hardware Engineer, System ArchitectFPGADeprecatedPrivate Only
Designing with the UltraScale and UltraScale+ ArchitecturesUltraScale+, UltraScale, Architecture, Clocking, DSPHardware Engineer, System ArchitectFPGACurrentPrivate Only
Designing with the Versal Adaptive SoC: Architecture and MethodologyArchitecture, Tools, Simulation, Debugging, Versal, PetaLinuxHardware Engineer, Software Engineer, System ArchitectFPGA, Adaptive SoC, SoCDeprecatedPrivate Only
Designing with the Versal Adaptive SoC: Network on ChipArchitecture, Versal, Memory, I/O, DebuggingHardware Engineer, Software Engineer, System ArchitectAdaptive SoCCurrentPublic and Private
Designing with the Versal Adaptive SoC: Power and BoardSignal Integrity, Versal, PowerHardware Engineer, System ArchitectAdaptive SoCCurrentPrivate Only
Designing with the Versal Adaptive SoC: ArchitectureArchitecture, Tools, Simulation, Debugging, Versal, PetaLinuxHardware Engineer, Software Engineer, System ArchitectFPGA, Adaptive SoC, SoCCurrentPublic and Private
Designing with the Versal Adaptive SoC: Hardware DebugAdaptive SoCCurrentComing soon
Designing with the Versal Adaptive SoC: Memory InterfacesAdaptive SoCCurrentComing soon
Designing with the Versal Adaptive SoC: Quick StartAdaptive SoCCurrentComing soon
Designing with the Versal Adaptive SoC: Serial TransceiversAdaptive SoCCurrentComing soon
Designing with the Versal AI Engine: Quick StartAdaptive SoCCurrentComing soon
Designing with the Versal Apative SoC: PCI Express SystemsPCIe, AXI, Embedded, ConnectivityHardware Engineer, Software Engineer, System ArchitectAdaptive SoCCurrentPrivate Only
Designing with the Xilinx 7 Series FamiliesArchitecture, Clocking, DSPHardware Engineer, System ArchitectFPGA, SoCDeprecatedPrivate Only
Designing with the Zynq UltraScale+ RFSoCRFSoC, Simulation, Zynq UltraScale+Hardware Engineer, Software Engineer, System ArchitectFPGA, SoCCurrentPublic and Private
Designing with UltraScale FPGA TransceiversSignal Integrity, Testbench, DebuggingHardware EngineerFPGADeprecatedPrivate Only
Designing with VerilogRTL, Testbench, Simulation, LanguageHardware Engineer, System ArchitectFPGACurrentPublic and Private
Designing with Versal AI Engine: Architecture and Design Flow -1Versal, Architecture, Tools, EmbeddedHardware Engineer, Software Engineer, System ArchitectAdaptive SoC, AICurrentPublic and Private
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2Versal, Tools, Debugging, EmbeddedSoftware Engineer, System ArchitectAdaptive SoC, AICurrentPublic and Private
Designing with Versal AI Engine: Kernel Programming and Optimization - 3Versal, Debugging, EmbeddedSoftware Engineer, System ArchitectAdaptive SoC, AICurrentPublic and Private
Designing with VHDLRTL, Testbench, Simulation, LanguageHardware Engineer, System ArchitectFPGACurrentPublic and Private
Designing with Xilinx Serial TransceiversSignal Integrity, Testbench, DebuggingHardware EngineerFPGACurrentPrivate Only
Developing AI Inference Solutions with the Vitis AI PlatformVitis, MLSoftware EngineerAdaptive SoC, AICurrentPrivate Only
Developing and Optimizing Applications Using the OpenCL Framework for FPGAsOpenCL, Debugging, EmbeddedHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecatedPrivate Only
Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer FrameworkFPGA, SoCCurrentComing soon
DSP Design Using System GeneratorDSP, Tools, Verification, SimulationHardware Engineer, System ArchitectFPGADeprecatedPrivate Only
Dynamic Function eXchange (DFX) Using the Vivado Design SuiteTools, Debugging, partial reconfigurationHardware EngineerFPGACurrentPublic and Private
Embedded Design with PetaLinux ToolsZynq UltraScale+, MPSoC, Versal, Embedded, Tools, DebuggingSoftware Engineer, System ArchitectSoCCurrentPublic and Private
Embedded Systems DesignEmbedded, Zynq, Vivado, Tools, SimulationHardware Engineer, Software Engineer, System ArchitectFPGA, SoCCurrentPrivate Only
Embedded Systems Hardware Design Boot Camp for the MPSoC (BLT Exclusive)Vivado, MPSoC, Zynq UltraScale+, Debugging, ToolsHardware Engineer, Software Engineer, System ArchitectSoCCurrentPublic and Private
Embedded Systems Software DesignEmbedded, Zynq, Vivado, Tools, DebuggingSoftware EngineerSoCCurrentPrivate Only
Essential DSP Design Techniques using System Generator (BLT Exclusive)DSP, Tools, Verification, SimulationHardware Engineer, System ArchitectFPGADeprecatedPrivate Only
Essential DSP Implementation Techniques for Xilinx FPGAsDSP, Tools, Verification, SimulationHardware Engineer, System ArchitectFPGADeprecatedPrivate Only
High-Level Synthesis with the Vitis HLS ToolVitis, Tools, Testbench, Zynq UltraScale+, MPSoC, RTL, HLSHardware Engineer, Software Engineer, System ArchitectFPGA, SoCCurrentPublic and Private
How to Design a High-Speed Memory InterfaceMemory, I/O, Debugging, Tools, TestbenchHardware EngineerFPGADeprecatedPrivate Only
Intro to the Zync SoC ArchitectureFPGA, SoCCurrentComing soon
Migrating to the Vitis Embedded Software Development IDE WorkshopVitis, Tools, Debugging, EmbeddedHardware Engineer, Software Engineer, System ArchitectSoCCurrentPrivate Only
Operating Systems and Hypervisors in Adaptive SoCsProcessing, Linux, Hypervisor, AMP, PowerSoftware EngineerAdaptive SoC, SoCCurrentPrivate Only
PCIe Protocol OverviewPCIe, Debugging, Embedded, ConnectivityHardware Engineer, Software Engineer, System ArchitectFPGA, SoCDeprecatedPrivate Only
Signal Integrity and Board Design for Xilinx FPGAsSignal Integrity, Clocking, Simulation, VerificationHardware EngineerFPGADeprecatedPrivate Only
Spartan-6 / ISE User Migration Training (BLT Exclusive)Vivado, Tcl, Tools, Clocking, Debugging, Timing Constraints, SimulationHardware EngineerFPGACurrentPrivate Only
UltraFast Design MethodologyVivado, Tools, Timing Constraints, I/OHardware Engineer, System ArchitectFPGACurrentPublic and Private
UltraScale and UltraScale+ Architectures WorkshopFPGA, SoCCurrentComing soon
Using Alveo Cards to Accelerate Dynamic WorkloadsFPGACurrentComing soon
Using Robotics Applications with the Kria SOMKria SOMCurrentComing soon
Using Vision-based Applications with the Kria SOMArchitecture, Tools, AIHardware Engineer, Software EngineerFPGA, SOM, SoC, AICurrentPublic and Private
Verification with SystemVerilogRTL, LanguageHardware Engineer, System ArchitectFPGACurrentPrivate Only
Vitis Model Composer: A MATLAB and Simulink-based Product with DSP TechniquesVitis, DSP, HLS, AI, MATLABHardware Engineer, System ArchitectFPGA, Adaptive SoC, AICurrentPublic and Private
Vivado Boot Camp for the FPGA User Phase 1: FPGA Essentials - Architecture, Memory and IO (BLT Exclusive)Architecture, Memory, I/O, Clocking, Ultrascale, ToolsHardware EngineerFPGADeprecatedPrivate Only
Vivado Boot Camp for the FPGA User Phase 2: Tcl Scripting, IP Creation and Debugging (BLT Exclusive)Vivado, Tcl, Tools, Clocking, Debugging, Timing Constraints, SimulationHardware EngineerFPGADeprecatedPrivate Only
Vivado Boot Camp for the FPGA User Phase 3: Floorplanning and Advanced Timing Closure (BLT Exclusive)eVivado, Timing Constraints, Clocking, DebuggingHardware EngineerFPGADeprecatedPrivate Only
Vivado Boot Camp: Basic Training (BLT Exclusive)Architecture, Vivado, Tools, Timing ConstraintsHardware EngineerFPGADeprecatedPrivate Only
Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software UsersVivado, Tools, Timing Constraints, TclHardware EngineerFPGADeprecatedPrivate Only
Vivado Design Suite for ISE Software Project Navigator UsersVivado, Tools, Simulation, Timing ConstraintsHardware EngineerFPGADeprecatedPrivate Only
Xilinx for ManagersArchitecture, Tools, MethodologiesManagerFPGA, SoC, Adaptive SoCDeprecatedPrivate Only
Xilinx Partial Reconfiguration Tools & TechniquesTools, Debugging, Partial ReconfigurationHardware EngineerFPGADeprecatedPrivate Only
Zynq SoC System ArchitectureZynq, Memory, I/O, ArchitectureHardware Engineer, Software Engineer, System ArchitectFPGA, SoCCurrentPrivate Only
Zynq UltraScale+ MPSoC for the Hardware DesignerZynq UltraScale+, MPSoC, Tools, VivadoHardware EngineerFPGA, SoCCurrentPrivate Only
Zynq UltraScale+ MPSoC for the Software DeveloperZynq UltraScale+, MPSoC, Embedded, Tools, DebuggingSoftware EngineerSoCDeprecatedPrivate Only
Zynq UltraScale+ MPSoC for the System ArchitectZynq UltraScale+, MPSoC, Embedded, Tools, DebuggingSystem ArchitectFPGA, SoCDeprecatedPrivate Only
Zynq UltraScale+ MPSoC: Boot and Platform ManagementFPGA, SoCCurrentComing soon
Designing with the Versal Adaptive SoC: Design MethodologyMethodologies, Power, Tools, Timing Closure, DebuggingHardware Engineer, Software Engineer, System ArchitectFPGA, Adaptive SoCCurrentComing Soon

*Classes listed as “Public” are scheduled on our Calendar. Please view the Calendar for class dates. All other classes are available as private. Most deprecated classes have a current equivalent, and we would recommend taking the new class in most circumstances. Please contact BLT Training with questions.

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

Student from Vivado Boot Camp for the FPGA User Phase 3

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

Student from Designing with VDHL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

Student from Designing with VHDL